High Speed and Complexity,
Low Noise

No longer does the designer have the luxury of solving all signal problems by just terminating the critical clock traces or looking at simple signal delays and de-skewing the circuits with minor layout changes. With the rapid push toward higher integrated circuit miniaturization and system performance today, the board-level designer must take into account many factors that have never before been problematic in PCB designs.

These new design issues are a consequence of increasingly dense integrated circuit designs that operate at ever-faster internal clock and data speeds.

Internal processor clock speeds, for example, have doubled every 18 months for the past 15 years,¹ and I/O subsystems have increased at nearly the same rate. External parallel bus speeds are moving into the 500 MHz range.² On- and off-board serial communications are also beginning to extend beyond 4 Gb/sec.

In fact, the Fibre-Channel ANSI Standard x.3230 (FC-PH) has defined the physical I/O rate at more than 4 Gb/sec. Several device vendors are now developing products that will transmit and receive data at or even beyond this speed.

Printed circuit technology has been in existence for nearly 50 years. Multilayer circuit boards have been fabricated since the 1960s and are used extensively today in computers and other systems that are operated with integrated circuits and ASICs. It is a tribute to the flexibility of PCBs that they have been able to meet the demands of a wide variety of rapidly changing industries for the past five decades. This longevity is even more remarkable considering that
PCB technology has not changed substantially in the past 40 years.

However, the recent increases in on-board signal speeds may be about to change the unquestioned dominance of PCB designs for data transmission. The demand for very high data rates is causing signal integrity and noise problems that many PCB designers are finding difficult or impossible to eliminate in complex PCBs.

DWT, which is also called multiwire technology, offers several advantages to circuit designers of high-speed circuits. In very fast data-rate designs, the DWT configuration (see illustration) can remarkably reduce noise and improve signal integrity.

In DWT, wire is ultrasonically bonded onto the dielectric substrate. This technique offers tighter tolerances and more flexible, dense designs than PCB construction does (see Table I).

DWT is actually nearly as old as PCB technology, but there are a few reasons DWT has not become as widely used as PCB design has. For example, DWT requires higher costs than PCBs do for large production runs, and there is a small DWT vendor base, which may discourage some manufacturers from investing in it.

But as signal speeds continue to increase, DWT is beginning to appear a more attractive alternative to PCBs.

PCB Problem: Higher Speed, Higher Noise

There are a few methods that PCB designers have used to deal with the issue of signal timing. One is to decrease the voltage level of the signal (see Figure 1c). This method increases the signal timing margins and alleviates some of the potential data integrity problems. However, it also leaves system noise levels unchanged (see Figure 1d). Therefore, with lower signal-to-noise margins, overall signal integrity may be compromised, which may eventually jeopardize the data.

Another technique that designers have used to ensure larger signal timing margins is to increase the signal edge rates without lowering the signal voltage (see Figure 1e). This method may increase system noise and affect the signal timing and waveshape at the board level. Faster edge rates create larger voltage drops across the interconnect parasitics (the lead frames of devices and circuit board traces), which in turn can increase system noise levels on the power and ground planes.

Figure 1. If a signal clock pulse is doubled and signal edge rate is not decreased, signal timing problems can result (b). Although the signal voltage can be lowered to alleviate the timing problems (c), system noise levels will be unchanged (d). Another way to fix timing problems is to increase the signal edge rates without lowering voltage (e)

A closer look at the DWT configuration.

Handling system noise and circuit parasitics can be very difficult, especially in complex designs. The sources of system noise at the board level can be difficult to pinpoint as well as control. Simultaneous switching noise (often termed ground bounce), improper board grounding, crosstalk, or other electromagnetic system-level coupling to either the signal traces or power and ground planes can increase board-level noise and affect the signals and data communication paths on the board.

Circuit parasitics are introduced every time a trace is routed between two devices. These circuit elements are required for communication between two devices on a PCB or on an actual device substrate. If noise is primarily due to interconnect parasitics, a PCB designer has few options other than to attempt to reduce the use of parasitics as much as possible.

Figure 2. PCB traces are etched away from solid copper planes on the substrate (a). DWT traces are made by routing wire directly onto the substrate (b).

DWT Advantages

Minimized coupling and vias. In multilayer PCBs, traces often have to be routed in an x-y or Manhattan fashion to reduce coupling between signal traces on adjacent layers. Interconnection between layers is accomplished through drilled plated holes or vias, which connect one signal trace to another.

Figure 3. Cross-section of discrete-wire trace. Discrete wires can be routed in non-Manhattan configuration.

Discrete wires can be routed on top of one another in non-Manhattan configurations with minimal coupling (Figure 3), and non-Manhattan designs allow short interconnect paths. Also, in typical DWT designs a single wire is used across the circuit paths, so vias are often required only at the ends of the paths. This reduction in vias along circuit paths reduces the distortion of high-speed signals due to vias.

Figures 4a and 4b. When one wire is routed over another, a small amount of coupling occurs. The DWT stripline configuration shown in Figure 4a includes only the active trace (AT) with a voltage source. Figure 4b also showns a passive victim trace (VT) crossing the AT at 70°.

When a wire is routed over another wire, some coupling does occur (see Figure 4a, 4b, 4c, and 4d). The coupling between the traces is capacitive and is typically very small (on the order of 0.025 pF per crossover). This coupling is typically at least 20 times smaller than the amount of capacitance from a typical signal via interconnecting two pieces of etch from one layer to the other.

Figure 4c. The input impedance Zin of the active trace shown in Figures 4a and 4b is plotted for a frequency range of a few kilohertz to 450 MHz. As the diagram shows, the coupling between the traces is capacitive and very small (on the order of 0.025 pF per crossover).

With the small amount of coupling, many wires can cross over or under each other before capacitance becomes significant.

Improved propagation speed. Another electrical advantage of DWT over PCB design is better propagation speed and delay across the board.

Figure 4d. The spatial distribution of the surface current induced on the bottom plane of the DWT board shown in Figure 4b for a frequency greater than 100 MHz.

In DWT designs, each wire is surrounded with dielectric insulation. The wire is also embedded slightly into the surrounding dielectric substrate (see Figure 5). The effective dielectric constant (e_r) is approximately 3.3 (this is the relative dielectric constant of the insulation around the wire and of the circuit board substrate that surrounds the wire). Typical fiberglass substrates have dielectric constants of approximately 4.0. Discrete wire traces offer a 10% reduction in propagation delay over etched traces. In addition, the reduction in via count along the interconnect path in DWT designs also increases signal velocity. These speed enhancements, combined with the ability to route traces at angles and in non-Manhattan fashion, reduce DWT interconnect propagation delay 50% or more compared to PCB designs. This delay improvement can be critical to the system designer who is trying to build a very fast interconnect between two devices, such as a bus on a circuit board.

Reduced crosstalk. A common problem of printed wire structures is crosstalk, the unwanted electromagnetic coupling between three or more conductors. If a high-speed signal couples to an adjacent clock trace that is sensitive to noise, signal and data integrity may be compromised. Also, if that adjacent trace is connected to a cable or other board, EMI may be generated, which can cause the system to fail FCC regulations.

Printed circuit wires often must be routed in parallel and close to each other because of system-level constraints, such as cost, skew, or a limited number of layers available. DWT can offer the board designer the option of routing critical wires further apart to reduce crosstalk.

Figure 5. Discrete wires are coated with dielectric insulation and slightly embedded into the dielectric substrate.

Smaller, denser circuit boards. DWT also offers mechanical advantages over PCB designs. Because DWT boards can be routed often on a single layer, they can be as much as 40% thinner than a comparable multilayered PCB. The density of the DWT routing layers is also often much higher than that of printed wire constructions. In DWT designs, wires can be layered over each other in complex configurations with routing densities of greater than 160 wires per square inch. Greater routing density can mean reduced circuit board dimensions.