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Modeling Varistors with
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| Figure 1. Basic structure of varistor model for simulation with PSpice. |
To create a model with PSpice, the
varistor is replaced by a current-voltage
characteristic, a parallel capacitance, and
a series inductance (Figure 1). The current-voltage
characteristic is simulated by a controlled
voltage source V, which is a function of current
I. An additional series resistance R2
of 100 µ
,
which is not visible in the basic configuration,
is inserted into the model. The current-voltage
characteristic prevents invalid conditions
from arising as a result of connection of
ideal sources in parallel or direct connection
of the varistor model to a source. This can
be described mathematically by the following
approximation:
log V = b1 + b2 x log(I) + b3 x e-log(I) + b4 x log(I) when I > 0
The characteristic for a particular varistor can therefore be described by parameters b1 to b4. The typical V/I characteristic for the varistor we used for modeling and its associated parameters are shown in Figure 2. The characteristic can move within its tolerance range defined by the specified varistor voltage. The standard tolerance for varistors is 10%. The tolerance range can be simulated with the parameter TOL by shifting the mean varistor characteristic. The typical characteristic (middle curve) is obtained when TOL is zero. The upper curve relates to a varistor voltage tolerance of +10% (TOL=10) and corresponds to the curve shown in the manufacturer's data book for the maximum protection level. The lower curve relates to a tolerance of 10% (TOL=10) and corresponds to the curve shown in the data book for maximum leakage current at currents up to 1 mA.
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| Figure 2. V/I characteristic of the varistor studied, with ±10% tolerance band. |
The typical capacitance given in the manufacturer's data book is inserted into the model. We ignored the slight variation of capacitance with the voltage applied and frequency for this study. The inductance of the varistor, on the other hand, must not be ignored in applications with steep pulse edges. It is therefore covered by a series inductance and largely determined by the inductance in the leads attached to the ceramic disk. On the other hand, the internal inductance of the zinc oxide varistor can be ignored. The inductance values covered in the model library apply to typical varistor mountings. An inductance of about 13 nH is obtained for the varistor studied. Longer varistor leads can be modeled by inserting additional inductances into the simulation circuit. The specific inductance of the leads of disk varistors is about 1 nH per millimeter.
The Limits of Modeling
For mathematical reasons, the V/I
characteristic is extended in both directions
beyond the current range (10 µ to
Imax) specified
in the data book and is not limited by PSpice.
If the simulation exceeds these limits, the
model loses validity. Values of less than
10 µ
can therefore lead to incorrect simulation
results, but do not endanger the real component.
Moreover, exact knowledge of leakage currents
in the range of up to 10 µ
is only required in exceptional cases for
varistor applications. But confidence in values
above the type-specific surge current Imax
can lead to destruction of the real component
as well as falsification of the result. What's
more, the varistor model does not check compliance
with other limit values, such as maximum continuous
power or pulse derating. Therefore this compliance
must always be verified against the figures
in the data book as well as by simulation.
Zinc oxide varistors have a negative temperature coefficient of voltage. This coefficient, TK, is equal to 0.05% K and decreases as current density increases. However, this relationship is not reproduced in the model because it has negligible influence on the protection level of the varistor.
Pulse Test Simulation
A test pulse of 10/700 µs duration as
specified by CCITT or IEC 1000-4-5 is often
used to check interference immunity of telecommunications
equipment. The test pulse is defined by the
test generator circuit and the given open-circuit
voltage. For an open-circuit voltage of 2
kV, the charging capacitor must be charged
up to 2.05 kV. An additional resistance R1
of 10 M
is inserted at the output to prevent undefined
floating of Rm2.
For worst-case simulation, i.e., the maximum protection level, the tolerance of the upper characteristic (TOL = 10) is used for the varistor. There is no need to simulate the equipment to be protected because it can be regarded as high impedance with respect to the varistor when the test pulse is applied. The curves calculated (Figure 3) show that the varistor can reduce the interference voltage at the equipment connected to 2 kV to less than 260 V. For a maximum current Imax of 44 A and integral idt of 17 mAs, the time tr required for an equivalent area rectangle is 386 µs (17 mAs ÷ 44 A). The derating field for the varistor studied (Figure 4) shows that with this value and at the maximum current Imax, ten pulse loads can be applied.
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| Figure 3. Simulation results: a) Test pulse simulation. b) Curve of voltage at varistor, current through varistor and current-time integral idt. |
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| Figure 4. Ten pulse loads can be applied at maximum current to the varistor studied. |
PSpice can also determine the energy absorbed by the varistor with the formula W=vidt, in this case 4.2 J. In conjunction with the varistor's maximum continuous power-handling capacity, Pmax, of 0.4 W, the minimum pulse interval, Tmin, can be determined as follows: Tmin = W/Pmax = 4.2 J/0.4 W = 10.5 s.
Since ten pulses with a duration of 10/700 µs applied at one-minute intervals are specified for telecommunications equipment, the varistor studied is suitable for this application.
Whether the varistor's operating voltage of 95 Vrms is suitable for the application depends on the protection level required for the equipment as well as the operating voltage (e.g., dc supply voltage, ringing tone voltage). If required, lower protection levels can be obtained by using a lower operating voltage or a larger-diameter varistor. However, designers should always make sure that the maximum operating voltage is equal to or less than the maximum operating voltage of the varistor.
Manfred Holzer studied engineering at Gratz University of Technology and has been designing varistors at Siemens Matsushita Components since 1990. Willi Zapsky studied telecommunications at Niederrheim Polytechnic and joined Siemens in 1973 as a designer of hybrid circuits. Since 1992 Zapsky has been marketing varistors for Siemens Matsushita Components.