The Effects of Some PCB Design Compromises on Clock Signals

Rick McMurray

Via slots, split planes, gaps, and other sometimes-unavoidable violations of design perfection affect trace impedance in ways that can be anticipated and mitigated.

Figure 1. The experimental PCB (click to enlarge).

An experiment was conducted to illustrate some basic design considerations for clock traces with respect to the slots that are created by adjacent vias, split planes, gaps in planes, and return paths. To minimize loop area—that is, to keep the return path for high-speed and other critical signals as short as possible—is a practice commonly taught. The experiment investigated some of the situations that the printed-circuit-board (PCB) design engineer might face when laying out a board, with a particular interest in what actually happens if the designer must compromise good design techniques because of some physical constraint. The primary intention was to see how each design compromise affected overall electromagnetic emissions.

This article briefly describes the experimental findings and also suggests ways in which undesirable situations can be altered in order to possibly improve signal transmission.

Experimental

An 8753D network analyzer from Agilent Technologies Co. (Palo Alto, CA) was used to take measurements during the experiment. A network analyzer is a device that can measure various characteristics of both passive and active components, such as the impedance of a trace or transmission line. Network analyzers typically include a signal source that is used as a stimulus for the device under test, and feature an input measurement port by means of which data are collected.

Figure 2. A plot of trace impedance versus distance for the ideally routed trace 1 (click to enlarge).

The PCB designed for the experiment consisted of six individual sections, labeled as traces 1 through 6 in Figure 1. The figure shows the bottom side of the PCB. Each section consisted of a 50-MHz oscillator driving a trace. In addition, the PCB had pads for three passive components. These pads were included in the design to accommodate future experimentation, but were not used in the experiment reported here, except for a 0-ž resistor in the location for a series resistor in the clock line.

The PCB was constructed as a two-layer, 0.062-in.-thick board. The signal traces and power distribution were on the top layer. For traces 1–4, the bottom layer consisted of individual copper fills that acted as ground planes. On traces 5 and 6, the return path was a trace on the bottom side. Traces 4–6 also were for future experimentation, and are not discussed here.
The power and ground for each section could be completely isolated from the other sections by the removal of jumpers. This was done so that, when measurements were taken on a specific trace, the results would not be influenced by the other oscillators coupling back through the power and ground.

Results and Discussion

Each section of the board, other than trace 1, illustrates a situation to be avoided, if possible. Trace 1 represents an ideal situation. In that case, the ground plane under the trace is complete for the entire length of the trace from the output of the oscillator to the output connector. The trace should maintain a constant impedance for its entire length.

Figure 3. A plot of trace impedance versus distance for trace 3, with marker 1 indicating the point at which the trace crosses a gap in the ground plane (click to enlarge).

Figure 2 is a plot from the network analyzer showing trace impedance versus distance for trace 1. Marker 1 indicates a large impedance mismatch due to the output BNC connector. Marker 2 shows a slight mismatch due to the series 0-ž resistor, and marker 3 shows another slight mismatch due to the output of the 50-MHz oscillator. The point to take from this figure is that the trace maintains a relatively constant impedance between the 0-ž resistor and the output connector.

Trace 2, as can be seen in Figure 1, runs over a slot in the ground plane. This slot was created by adjacent vias that did not have clearance sufficient to allow the copper fill to penetrate and connect between them. A slight impedance mismatch would be expected to occur where the trace goes over the slot. The slot in effect forces the return current to take a slightly longer path than is the case with the return currents in trace 1.

Trace 3 in Figure 1 exemplifies the situation in which a trace goes over a gap between adjacent planes. This situation could occur in a design that has multiple voltage planes on a single power layer, or where it is necessary to have different ground planes on a single layer—possibly analog and digital grounds. The experimental trace is a more drastic example of a slot. Basically, it is a slot that is infinitely long.

Figure 3 is the impedance-versus-distance plot for trace 3. This plot illustrates the same impedance mismatches as in Figure 2, but with one significant addition. The mismatch indicated by marker 1 in Figure 3 is the impedance mismatch caused by the clock trace crossing the gap in the ground plane. (The plot for trace 2 had a similar mismatch due to the slot there, but it was not as drastic.)

The situations represented by traces 2 and 3 in the experiment occur frequently. Design engineers typically encounter this situation when they are concentrating on getting the critical signals routed. Engineers must address via placement both with respect to the signal layers on which they are currently working and on the planes to which those vias are connecting. This ensures that large slots in the ground and power planes are not created by adjacent vias. They will then have to go back and rework those sections to try to adjust the via placement.

A good idea, when working on a PCB design, is to periodically inspect the power and ground planes so that the routing does not get too dense. Also, this makes it easier to adjust the vias in order to remove or minimize the slots.

But there is a trade-off that comes with trying to remove slots. A principal objective in making a connection to ground or power is to keep the trace running from the component to the via as short as possible in order to minimize trace inductance. Often, however, keeping the length short results in a row of vias that makes a slot in the plane. An engineer who always keeps in mind the need to avoid slots can avoid this, many times. It is often possible to come off a pad in a different direction and still keep the trace length short.

If the design ends up with slots that cannot be avoided, the engineer may be able to manually stitch the spaces between the vias with copper and still meet the design rules.

Conclusion

Designing PCB clock traces is a matter of balancing the ideal and the possible. Measurement of electromagnetic interference generated by certain design accidents has provided insight into the effects of careless or casual design, and suggests that vigilance should be an element of any design engineer’s toolkit.

Rick McMurray is vice president of Rhein Tech Laboratories (Herndon, VA), a firm offering services in electromagnetic interference testing and engineering, wireless testing, electrical safety testing, PCB design, and hardware design engineering. He can be reached at 703-689-0368.