Implementation Strategies for USB Circuit Protection Technology

Adrian Mikolajczak
Understanding the USB specification is key to selecting the proper circuit protection devices.

The USB specification requires current limiting and power switching for USB power management. The specification references resettable polymeric positive- temperature-coefficient (PPTC) devices and solid-state switches as acceptable methods of overcurrent protection. Like fuses, PPTC devices help protect circuitry from overcurrent damage.

Unlike fuses, however, PPTC devices reset when the circuit is de-energized and the fault is removed. In addition to their resettability, the critical design advantages of these devices in USB applications are low resistance, fast time-to-trip, low tripped power dissipation, and inherent resistance to nuisance tripping. They also help provide a lower-cost solution than silicon equivalents.

Protected power-switch devices integrate current-limiting functionality with power switching. These devices are most commonly used in bus-powered hubs, dual-mode hubs, and low-power hosts. They can also function as inrush-current-limiting devices. They combine low resistance with extremely fast current-limiting capability. Such devices are a practical, cost-effective solution for power-constrained hosts, where a fast current-limiting response further reduces system voltage droop in a fault condition and where power switching can be used to improve energy conservation.

Industry Specification Requirements

The USB specification states that current limiting, power switching, or both may be required in a USB product, as shown in Table I. Where current limiting is required, the UL 60950 specifications must be met. This means that in the event of a short circuit or other fault condition, current output must be limited to below 5 A within 60 seconds. The USB specification also defines acceptable voltage output levels and limits total voltage drop in the system.

PPTC Device Technology

PPTC circuit-protection devices are made from a composite of semicrystalline polymer and conductive particles. At normal temperatures, the conductive particles form low-resistance networks in the polymer (see Figure 1). However, if the temperature rises above the device's switching temperature (T_Sw), either from high current through the part or from an increase in the ambient temperature, the crystallites in the polymer melt and become amorphous. The increase in volume during melting of the crystalline phase causes a hydraulic separation of the conductive particles and results in a large nonlinear increase in the resistance of the device.

The resistance can increase by three or more decades. This increased resistance protects the equipment in the circuit by reducing the amount of current that can flow under the fault condition to a low, steady-state level. When the device transitions to the high-resistance state, it is said to have "tripped." The device will remain in its tripped (high-resistance) position until the fault is cleared and power to the circuit is removed—at which time the conductive composite cools and recrystallizes, restoring the PPTC to a low-resistance state in the circuit and returning the affected equipment to normal operating conditions.

PPTC devices are typically used in USB hosts and in USB self-powered hubs. The resettable current-limiting devices are placed in series with the output power port of a USB device. Current limiting in a fault condition helps prevent circuit damage and systemwide voltage droops. With individual port protection, it allows the remainder of the USB bus to continue functioning even if one port is short-circuited. As shown in Figure 2, the critical device parameters in USB applications include time-to-trip, resistance, and power dissipation.

PPTC devices are resistive series elements on the USB power bus. Resistance, unless otherwise stated, applies to a device when it is not in the tripped state. As such, the lower the PPTC device resistance, the lower the voltage drop between the power supply and the USB output pin during normal device operation. In bus-powered hub applications, voltage drop must be less than 0.1 V, which means that total resistance, including all series elements and the board traces, must be less than 1 W (at 100 mA). In hosts and self-powered hubs, no voltage drop is specified; it is dictated instead by the requirement that the output voltage be 4.75 V minimum.

Hold current is the highest steady-state current that a device will maintain for an indefinite period without tripping. Hold current is temperature dependent, and the designer must consider the maximum ambient temperature that the device will be exposed to. Generally speaking, lower hold currents imply higher resistance and faster trip time, and higher hold currents offer lower resistance. For low-power applications, a device with the lowest possible hold current should be selected.

Time-to-trip characterizes the speed at which a PPTC device will trip in a fault condition. Time-to-trip is critical in low-power applications because a small power supply may only be able to source short-circuit currents for short periods before the overall system voltage is reduced (or droops) and system operation is affected. Time-to-trip values are highly dependent on device design, device size, and hold current. These values can also be influenced by board layout, where large trace sizes or pads functioning as heat sinks will increase time-to-trip. Reducing pad sizes and selecting a device with a low hold current can improve time-to-trip results.

USB Device Overcurrent Protection1 Power Switching1 Host controller Required Optional Self-powered hub Required Optional Bus-powered hub Optional Required Dual-mode hub2 Required Required 1. May be designed on either a ganged or individual-port basis. 2. Dual-mode hubs can function as both powered or bus-powered hubs.

Table I. Circuit protection and power-switching requirements for USB.

Tripped power dissipation, or leakage current, is another important consideration for low-power designs. After a PPTC device is tripped, it will stay latched in a high-resistance state, continuing to pass a small trickle current (dissipate power) until it exits the tripped state. The lower this trickle current, the lower the power drain on the system during a fault condition.

Protected Power-Switch Technology

Protected power-switch devices are silicon series elements used in the USB power bus to control the flow of power to ports and to help protect circuitry and devices from overcurrent conditions. Like the PPTC device, the protected power switch trips in an overcurrent condition, but it does so in a two-phased approach. The device trips in microseconds, limiting current to a predefined range that is higher than nominal operating current. It then flags the controller that a fault condition has occurred. The controller can then shut down the port by toggling the enable pin on the power switch. If the controller does not respond, the power switch cycles the port on and off to prevent internal thermal damage.

The critical device parameters in USB applications include switch resistance, continuous output current, time-to-trip, current-limit set point, fault-flag delay, current-limit release point, and tripped current draw.

Switch resistance can affect both system power draw and the end-user experience. This resistance is measured through the device when it is not in current-limiting mode. High switch resistance can result in excessive voltage drop through the device, which can result in USB noncompliance and the device functioning improperly. Silicon switch resistance can be a function of supply voltage, and the best device will minimize resistance and voltage drop at lower bus voltages in order to maintain USB output voltage compliance.

Continuous output current is the current level at which the device will not trip. For low-power applications, this current should be set as low as possible while still supporting the USB specification.

Time-to-trip defines the speed at which a protected power- switch device activates its current-limiting circuitry. The extremely fast time-to-trip of the silicon device makes it the preferred choice for power-constrained applications. Unlike the PPTC device, however, posttrip current levels can remain fairly high and are defined by the current-limit set point. The current-limit set point is the level at which a silicon device will limit current once it has tripped. Its value varies depending on the severity of the fault condition. The value is typically defined as a function of the fault condition's resistance. For low-power applications, the current limit should be specified as low as possible.

Integrating a fault-flag delay with the silicon device helps prevent nuisance tripping and improves the end-user experience. The fault flag is a logic-level output that alerts the USB controller when there is a problem with a specific USB port. During USB hot-plug events, many USB functions are highly capacitive and can draw significant current, exceeding specification limits. This increased draw of current causes the device to trigger a short-lived current-limiting condition that, if signaled to the controller, will cause nuisance tripping. As shown in Figure 3, a 9-millisecond fault-flag delay prevents these short-lived events from triggering the fault flag.

The current-limiting release point is a critical parameter for the end-user experience. This is the current level at which the silicon device will disengage its current-limiting function. This is an important design consideration because once current limiting is active, device resistance dramatically increases and may prevent proper functioning of an attached USB device. If set too low, a device that enters current-limiting mode during hot-plug may remain tripped when initial in-rush currents subside, preventing proper operation of USB functions. By setting current-limiting release points above 500 mA, the protected power switch will cease to limit current once the USB device returns to normal operating-current levels.

Initial power dissipated at the port after a trip event is a function of the silicon device's limit current. If the device can be turned off during a fault condition, port current draw and power draw are negligible. If, however, control circuitry is not implemented (i.e., the enable pin is tied high in a high-enable device or power switching is not integrated into the device), most silicon devices will continue to limit current until they reach an internal temperature threshold. When the temperature threshold is reached, they will begin to thermally cycle the port on and off. Average port current draw under these conditions will be a function of the thermal duty cycle and the current limit. For low-power applications using silicon devices, it is important to implement proper on-off control circuitry to prevent high tripped power dissipation.

Improve Reliability, Reduce Component Count

Protected power switches can integrate numerous detection and protection functions, resulting in improved performance and reduced component count. Figure 4 compares a typical silicon power switch to a protected power switch.

In a typical power-switch implementation, C_filter and R_filter are used to generate a delay in the fault-flag signal, whereas Raychem protected power switches integrate this feature and obviate the need for off-board circuitry. The fault-flag delay prevents inrush currents from causing the port to nuisance trip, and the attached device is able to begin normal operation. To further minimize external component count, the protected power switches integrate pull-up and pull-down resistors for the Enable and Flag pins (OC1 and OC2).

These protected power switches are designed so that the fault-flag outputs are set at complementary metal oxide semiconductor (CMOS) levels. This is critical for low-cost implementations, as some controllers cannot support 5-V inputs. By supporting a CMOS-level output, no external voltage-splitting network is required.

Figure 5. Independent overcurrent and overtemperature coordination.

The protected power switch also facilitates independent port protection to improve end-user experience. When a legitimate overcurrent condition is detected and the offending port is turned off, the remaining ports are unaffected. Figure 5 demonstrates independent port protection where a 1-W load is connected to Channel A to simulate a 5-A overcurrent condition, while a 185-mA continuous load is applied to Channel B to simulate normal device operation.

The power switch device detects the fault on Channel A and begins to limit current. On Channel A only, the protected power-switch device will eventually begin to cycle on and off until the fault is resolved. However, operation on channel B continues unaffected because its continuous load current is within specification.

This independent port-protection functionality also affects power consumption and allows limit points to be minimized to reduce the power drain in a fault condition. Because each port is protected individually, maximum expected currents are 500 mA and below, as opposed to ganged protection, where a single channel protects two ports at 1 A continuous current.

The ability to enable or disable a port is important in low-power applications. In a fault condition, a silicon device enters current-limit mode, preventing extreme current spikes and voltage droops, but it will continue to allow significant current to pass through the port. If the port cannot be disabled, the silicon device will eventually enter a thermal cycle mode. Cycling will reduce total power draw, but this draw can still be in excess of 1 W per channel. As shown in Figure 5, with the protected power switch, Channel A could be shut down by the controller, resulting in a port current draw on the order of 10 µA.

Figure 6. With the protected power-switch device, resistance decreases as input voltage decreases.

Another important consideration in USB designs is resistance drop with decreasing voltage. As the supply voltage decreases, voltage drop becomes increasingly critical. Typically, as voltage decreases, power switches increase in resistance—an undesirable characteristic. As depicted in Figure 6, the protected power-switch device resistance decreases as the supply voltage decreases. When bus voltage is high, this reduces output current to improve power efficiency and battery life. When the bus voltage is low, the voltage drop across the power switch is reduced, allowing the USB function to continue to operate for a longer period.

Conclusion

Resettable current limiting in a fault condition helps prevent circuit damage, systemwide voltage droops, and associated system failure. It also helps the system meet UL safety standards. Because PPTC devices are typically a low-cost current-limiting solution, they are frequently used in desktop hosts, laptops, and self-powered hubs. Individual port protection with PPTC devices can also enhance energy conservation and systemwide reliability.

Protected power-switch devices are most commonly used in bus-powered hubs, in dual-mode hubs, and in low-power hosts. They can also be used in USB functions as inrush-current-limiting devices. Protected power-switch devices integrate current-limiting functionality with power switching, and provide low resistance and extremely fast current-limiting features. These characteristics make them suitable for power-constrained hosts, where the addition of power switching can be used to achieve maximum energy conservation by shutting down a port that has experienced a fault.

Adrian Mikolajczak is multimedia market manager for Tyco Electronics Power Components, Raychem Circuit Protection Div. (Menlo Park, CA). He can be reached via e-mail at adrianm@tycoelectronics.com.