ESD Protection for High-Speed I/O Signals

Jeffrey Dunnihoo
It is critical to identify the I/O interface to be protected before selecting the ESD protection device.

An integrated circuit (IC) connected to external ports is susceptible to damaging electrostatic discharge (ESD) pulses from the operating environment and peripherals. The same ever-shrinking IC process technology that enables such high-port interconnect data rates can also suffer from higher ESD susceptibility because of its smaller fabrication geometry. Additional external protection devices can violate stringent signaling requirements, leaving design engineers with the need to balance performance and reliability.

Traditional methods of shunting ESD energy to protect ICs involves devices such as zener diodes, metal oxide varistors (MOVs), transient voltage suppression (TVS) diodes, and regular complementary metal oxide semiconductor (CMOS) or bipolar clamp diodes. However, at the much higher data rates of USB 2.0, IEEE 1394, and digital visual interface (DVI), the parasitic impedance of traditional protection devices can distort and deteriorate signal integrity. This article examines the general parameters designers should look for in ESD protection devices and how these specifications affect and protect their application.

ESD Basics

An ESD event is the transfer of energy between two bodies at different electrostatic potentials, either through contact or via an ionized ambient discharge (a spark). This transfer has been modeled in various standard circuit models for testing the compliance of device targets. The models typically use a capacitor charged to a given voltage, and then some form of current-limiting resistor (or ambient air condition) to transfer the energy pulse to the target. ESD protection devices attempt to divert this potentially damaging charge away from sensitive circuitry and protect the system from permanent damage, as shown in Figure 1.

ESD Device Specifications: What to Look For   Many vendors use completely different specification methods for ESD protection components, and a designer may often be forced to harvest comparable data points from dissimilar graphs and tables. Here are some common differentiators to look for and to ask vendors about their products. IEC Rating. Verify that the ESD protection device is guaranteed to meet or exceed specifications in IEC 61000-4-2. Contact versus Air Discharge. Be careful to compare identical specifications. Some devices are advertised with high air discharge ratings, which can be incorrectly compared with the normally lower contact discharge ratings. Contact ratings are fairly repeatable, whereas air ratings can vary. Clamp Voltage. Choose a device with a maximum clamp voltage at a given peak current well below the level that the protected devices can tolerate. The lower, the better. Pulse Current. Watch for sometimes misleading approximation of peak power capacity. It can usually be improved by specifying a shorter peak duration. Response Time. Faster-acting devices reduce the width of the pulse transferred, and these devices can help attenuate the peak clamp voltage. Parasitic Capacitance. Added capacitance degrades I/O signal rise and fall times. On lower-speed signals, this stray capacitance can be lumped into or can displace the need for EMI capacitors. Parasitic Inductance. Higher impedance in the clamp path (to VDD or ground) can increase the effective system clamp voltage. Multistrike Capability. Verify that the protection designed-in can survive the expected life of the system. Resultant field failures are difficult to diagnose and can manifest themselves in unexpected functional errors, or even data loss. Integration and Matching. High-speed differential signals, such as in IEEE 1394, benefit from matched loading on the positive and negative lines of each pair. ESD protection products with multiple devices per package (such as thin-film silicon) can have intrachip device-to-device parasitic impedance matching of less than 0.1%. Unitary packages, however, may vary as much as 30% interchip matching. Printed-circuit-board (PCB) signal routing restrictions may also indicate a need for tight multidevice integration.

Other environmental electronic hazards can also wreak temporary or permanent havoc on a system. Electrical fast transients (EFTs) and induced electromagnetic interference (EMI), or even lightning strikes, can produce similar damage or system failures. Each hazard requires a different approach for protection.

High-Speed ESD Protection

As IC manufacturers have achieved higher frequencies of input/output (I/O) interconnects, such as with USB 2.0, they have continued to decrease the minimum dimensions of the transistors, interconnections, and the silicon dioxide (SiO₂) insulation layers in their devices. This decrease results in smaller structures for higher-speed devices that are more susceptible to breakdown damage at lower energy levels. SiO₂ layers are more likely to rupture, and metal traces are more likely to open or bridge during an ESD event.

Figure 1. ESD protection devices attempt to divert a potentially damaging charge away from sensitive circuitry and protect the system from permanent damage.

The changing application environment is also contributing to increased ESD vulnerability. A proliferation of laptop computers and handheld devices such as cell phones, personal digital assistants (PDAs), and other mobile devices are being used in uncontrolled environments (i.e., no wrist-grounding straps or conductive and grounded table surfaces). In these environments, people are likely to touch I/O connector pins during the connecting and disconnecting of cables.

The traditional methods for shunting ESD energy away from the ICs involved devices such as zener diodes and MOVs that have moderate capacitances of 10 to 100 pF. Now with higher signal frequencies, these devices cannot be used without distorting the signal beyond recognition or detection.

Many ICs are designed with limited internal ESD protection, allowing them to tolerate from 1- to 2-kV pulses (per the human body model [HBM]), but some ICs are not capable of tolerating even 100 V without suffering damage. Many IC data sheets do not even specify an ESD tolerance voltage, so users must do their own testing to determine the tolerance of the IC. The creation of ESD charges also varies widely with ambient relative humidity (RH). Walking across a vinyl tile floor with more than 65% RH generates only 250 V of ESD; however, if the RH is less than 25%, normal in dry environments, electrostatic potentials of more than 12,000 V can be generated.

ESD Standards

Two popular standards are used to ensure uniform testing of devices for ESD tolerance: the HBM, which came from the U.S. MIL-STD-883 standard, and the more-stringent IEC 61000-4-2, which originated in Europe but is now used worldwide. The IEC standard requires the tester to store a charge 50% larger than the HBM and to discharge it through a resistor that is about one-fifth the size of the HBM resistor.

This results in a subnanosecond pulse rise time and a peak current many times larger. The highest direct-contact-to-the-pins ESD voltage of the IEC standard is 8 kV, which has become something of a de facto industry standard. Both standards use a prescribed pulse waveform that testers must duplicate.

ESD Protection Devices

A variety of technologies are used in devices for ESD protection.

Figure 2. A parasitic capacitor here is too high to pass high-frequency signals without significant distortion.

Zener Diodes. One traditional device, the zener diode, is generally poorly suited for very high-speed I/O interfaces because the lowest capacitance of existing devices is about 30 pF (shown as a parasitic capacitor in Figure 2). This capacitance is too high to pass high-frequency signals without significant distortion. This distortion results in unreliable detection of the signals and increased high-frequency roll-off. Zener diodes could be made with lower capacitances, but this would result in ESD voltages insufficient to meet the 6–8-kV protection levels necessary.

TVS Diodes. There are some TVS devices on the market that add a regular diode in series with the zener diode to effectively lower the net capacitance. To handle positive- and negative-polarity ESD pulses, a second zener and series diode pair (in the opposite polarity) must be placed in parallel with the first pair of diodes. Unfortunately, the resulting capacitance of 5–6 pF is still not low enough to avoid distortion of high-speed I/O signals.

MOVs. MOVs can achieve slightly lower capacitances than TVS devices, but currently the lowest-capacitance MOV device available has a capacitance of 3 pF, which can still exceed the allowable load on high-speed interconnects.

Figure 3. Regular diodes can be used to clamp the ESD pulses to the power or ground rail so the current flow is always in the diode's forward direction.

Dual-Rail Clamp Diodes. Zener diode capacitances are high because their structures must be sufficiently robust to tolerate reverse breakdown phenomena. To eliminate the need for the zener's breakdown, regular diodes can be used to clamp the ESD pulses to the power or ground rail. Using this solution, the current flow is always in the diode's forward direction, as shown in Figure 3. This setup allows the use of smaller, and therefore lower, capacitance diodes. Positive ESD pulses are clamped to the positive supply rail, and negative ESD pulses are clamped to ground. (The system-bypass capacitors and power supply are responsible for shunting this extra energy on the positive rail back to ground. This can sometimes be aided by also adding a local zener diode, which does not affect the signal load.)

At first glance, this scheme can be implemented with standard low-capacitance diodes. These diodes are cheap, readily available, and have a capacitance of 1.5 pF per diode (so the capacitance on the signal is 3 pF for the two diodes). However, this capacitance is relatively high, and an examination of the data sheets reveals that they were not designed for high-current ESD pulses. These diodes have no specifications that guarantee their use with the high current and voltages of ESD pulses or with repetitive high-current ESD pulses. Some will degrade and eventually fail at high ESD voltage and currents.

Polymer Devices. The polymer devices symbolized in Figure 3 have resistances that are voltage dependent. With a low voltage (e.g., 5 V), the impedance is in the gigohm realm. When a high voltage is applied across the polymer device, the resistance drops to a very low value, so that tens of amperes can be shunted to ground. What makes these polymers attractive for high-frequency applications is their sub-picofarad capacitance (0.05–1.0 pF). This low capacitance, however, comes with some not-so-attractive side effects.

Unlike zener diodes that break down at the same voltage that they clamp to, a polymer device does not break down until it reaches a voltage that is much higher than the final clamping voltage. A typical polymeric ESD device does not break down until as much as 1000 V is reached. Then it snaps back to a clamping voltage of up to 150 V. After the charge is dissipated, the polymer returns to its high-impedance state.

Consequently, polymer devices can be used only in applications in which the ICs that are supposed to be protected must have their own built-in ESD protection that can tolerate the breakdown or trigger voltage of the polymer device (trigger voltages vary from 300 to 1000 V; clamping voltages vary from 60 to 150 V). These devices can be difficult to accurately characterize in manufacturing, so their data sheets often contain only typical specifications without guaranteed minimums and maximums. So, there is a design caveat here. Additionally, because these are physically elastic devices, their performance degrades based on the number of ESD pulses they receive. Their specifications can only guarantee certain limits over a lifetime of a given number of ESD pulses. These lifetimes vary from 1000 pulses to as low as 20 pulses.

Metal Oxide Silicon (MOS) Devices. A new technology uses a dual-rail clamp configuration as shown in Figure 3. The process technology to make the diodes, however, is fundamentally different. PicoGuard technology is derived from a MOS process that is optimized for minimum capacitance. Traditional diode structures are derived from simple bipolar technologies and tend to have higher capacitance levels. The new technology is the first to combine low capacitance with low-voltage clamping levels and high ESD tolerance.

These diodes provide ESD protection beyond IEC 61000-4-2 (±8-kV-and-above contact) with a capacitance of <1.3 pF maximum (~1.0 pF typical). They have a low insertion loss (virtually zero up to 3 GHz) and a clamping voltage below 15 V (V_CC +10 V, ground –10 V) with no higher trigger voltages. Other specifications include a subnanosecond response time, durability of more than 1000 ESD pulses, and a leakage current of 1.0 µA.