Leo G. Henry

A comparison of two HBM standards identifies the technical differences so that a better choice can be made as to which to use for ESD stress testing.

Leo G. Henry

In an earlier article, this author made reference to the fact that there are several standards bodies that have published electrostatic discharge (ESD) standards for the ESD stress testing and qualification of integrated circuits (ICs) at the component level.¹ The existing ESD standards simulate the ESD events associated with the human body model (HBM), the machine model (MM), and the charged device model (CDM), respectively.^2–4 These standards bodies are the ESD Association (ESDA/ANSI), the Automotive Electronics Council (AEC), JEDEC/EIA (Electronics Industries Association), and RCJ/EIAJ (Reliability Center for Electronics Components of Japan).^2,5–7 Of course, those familiar with ESD testing will also be aware that the older 1989 HBM military standard, MIL-883E-Method 3015.7, is still being used today.⁸

Existing ESD Standards

The ESDA/ANSI combination simply means that the American National Standard Institute (ANSI) approves and publishes the ESDA standards instead of writing them itself. ESDA is an accredited ANSI standards developer, and the ANSI designation gives the ESDA standards instant recognition and credibility worldwide. Several questions come to mind. Which standard should we use, and which group do we believe? Why do we have so many bodies attempting to guide and influence the user as to what to do to qualify a product? Why isn't there just one standard for each ESD event type? In any standard, we should look for at least three things: guidance, specifications, and direction so that reproducibility and compatibility are maintained. With these parameters, the standard provides a level playing field. Let's consider the several existing HBM standards relative to what they are trying to accomplish.^2,5–8 To better understand the similarities and the differences between these documents, we will perform a Rosetta Stone analysis, which compares the specifications and procedures in the two documents.⁹ Standards for MM, CDM, and transmission line pulse (TLP) will be addressed in a future column.^3,4,10

It is not too far-fetched to say that the most important event in ESD stress testing is that a pulse or waveform from the ESD tester will be delivered to the device under test (DUT). This waveform must adhere to specific parameters, and the tester must be able to deliver this pulse consistently for the duration of the test. Therefore the standard must specify limits for both the waveform and the tester.

The Rosetta Stone Analysis

The Rosetta Stone process is used here to point to the similarities and differences between the 2001 ESDA HBM standard and the 1989 MIL standard for HBM (see Table I). These two standards were chosen simply because they both represent the most recently updated and the oldest existing HBM standards respectively. In addition, in both standards, the equipment types (ESD tester, scope, current probe, etc.) are somewhat similar. In some sections of the standards, however, the specifications are quite different, which leads to different tester parameters. This is most apparent in the observed waveforms and, subsequently, in the different failure levels for the same devices tested on a minimum of two different testers, each of which meets a different standard.^11,12 

The Oscilloscope

Both standards bodies agree that an oscilloscope with a minimum 350 MHz single-shot bandwidth (BW) is the appropriate tool to use to collect and display the waveform. This is good, but the waveform rise time (T_r) quoted in each standard is not the same. For the ESDA standard, the specified HBM event rise time range is 2–10 nanoseconds. The MIL standard quotes <10 nanoseconds (see line 13 of Table I). According to Hewlett-Packard, the 350 MHz is equivalent to a 1.0-nanosecond rise time scope measurement capability, where T_r (nanosecond) = 350/BW (MHz).¹³This is because the scope bandwidth should always exceed (i.e., be faster than) the bandwidth of the predominant frequencies of the pulse or signal being measured.The measuring probe should also always have a bandwidth greater (i.e., faster) than the scope by a factor of 3. In either case, the higher the bandwidth of the scope and probe, the less likely there will be error in the measurement.¹³ 

Current Probe and Cable Length

The HBM MIL standard is aligned with the ESDA HBM standard with respect to specifying 350 MHz as the minimum bandwidth capability of the current probe (CT-1, for example). However, the MIL standard does not specify an equivalent probe, and it does not provide a rise-time specification or a minimum current capability if indeed it becomes necessary to use an equivalent-type current probe. This is significant because of the relatively fast rise time (2–10 nanoseconds) and peak-current requirements for the waveform (pulse) in the HBM standard. Note, however, that the difference in the cable lengths of the current probes (see line 7 in Table I) of 1 m maximum for the ESDA standard and 0.91 m for the MIL standard is not significant relative to the measurement capability of the scope.

Waveforms

The general shape of the input pulse or waveform is a double exponential (see Figure 1) with a relatively fast rise time (2 nanoseconds) and a relatively long decay time out to 600 nanoseconds, which is about four time constants (¥ = RC) using the general decay equation I = I_o Exp (–t/RC). I is the final current, I_o is the initial current, t is the time, R is the resistance, and C is the capacitance. The good news is that both standards specify the same double exponential waveform shape.

Figure 1. Graph depicts the HBM double-exponential waveform through a shorting wire.2

Rise Time

Two of the more important waveform parameters are the rise time, T_r, and the peak current, I_p. The general rule of thumb is that rise time turns on device structures and peak current fails devices. The ESDA standard specifies a rise-time range of 2–10 nanoseconds for all voltage levels. The MIL standard, however, specifies simply <10 nanoseconds without setting a lower limit. This latter condition of no minimum can be problematic because there are published and unpublished data that show that the failure levels for devices tested using a simulator or tester with the lower rise-time range (2–5 nanoseconds) are different from the failure levels for those same devices tested on a simulator that produces the higher rise-time range (6–10 nanoseconds).¹⁴ This difference points to the need for a thorough rise-time specification. If rise time is not specified (as is the case with the MIL standard), then there will be an uncertainty with respect to device correlation between the testers. This miscorrelation was published for testers that had met the ESDA HBM standard and were then compared with data from testers that met the MIL standard. ¹¹ 

Peak Current and Ringing Current

For the peak current (I_p), a short wire (zero ohm) is used for current measurement at each voltage during the calibration, verification, or qualification of the ESD tester. However, the two standards use different methods for the actual I_p measurement. The ESDA method extrapolates the peak current from the exponential decaying portion of the waveform. In contrast, the MIL standard uses a peak position measurement method. Both measurement methods have drawbacks. Depending on the level of the tester parasitics, the resulting distorted waveforms do not always provide for an exact peak position. Further, too much overshoot (on I_p) and too much ringing (the higher-frequency oscillations superimposed on the normal waveform) not only prevent the exact location of a peak position but also cause the extrapolation to the peak current to become a small mathematical nightmare. Both standards, however, address the issue of excessive ringing by specifying that the ringing current, I_r, must be <15% of I_p, and the decrease in the ringing must be such that there is no ringing from the 100-nanosecond position and beyond.

Decay Time for the Zero-Ohm Test

The decay time, T_d, is another parameter that is extracted from the waveform. The significance of the decay-time measurements for both the zero-ohm (short wire) and the 500-W resistor can be misleading. For the zero-ohm measurement, both standards (see line 15 in Table I) agree on the established one-time-constant measurement position of 1/e, i.e., at 36.8% of I_p using the short wire. This value is 150± 20 nanoseconds and C = 100 pF (see Figure 3). Both standards agree that the measurement should start at I_p, which is the nonzero time position (x axis). Both also agree that the measurement should be done at all the stress levels for calibration and qualification of the tester. This is one of the few occasions when both standards are in total harmony for measurement of a significant waveform parameter.

500-W Resistance Measurement

During tester calibration and qualification, it is important that the tester provide the measured parameters that are as specified in the standards. The 500-W-load test is called an open load test because of its relative higher resistance value to the overall impedances (5–15-W) of the devices being tested. This test is called out in the ESDA standard because it shows how the parasitics in the tester affect the waveform produced. However, the MIL standard does not support this test. Therefore, equipment that follows the specifications in the MIL standard is questionable because the tester parasitics distort the specified waveform.

To justify the need to reduce tester parasitics, several research groups attempted to explain the HBM tester behavior in terms of rise time (T_r), decay time (T_d), ringing in the current (I_r), and peak current overshoot by using a simple equivalent-lumped circuit element (LEM) to model the elements in the HBM tester (see Figure 2).^{11,12,15–17}

Figure 2. The parasitic capacitances in the HBM ESD tester equivalent circuit.

Two published works showed that the 500-W-load test waveform had distortions when including the three acknowledged tester parasitics of shunt capacitor across the HBM resistor, the series inductance of the discharge path, and the test board capacitance (see Figure 2).^15,16

A third published work applied the complete 4th-order LEM circuit, which specifically addresses the influence of the tester board capacitances in addition to the socket and the socket adapter board capacitances (see Figure 2).¹¹ They used the raw data from the testers (nine total) to successfully extract the tester parameters, including the test board capacitances that measured between 12 and 95 pF for the nine different testers. The researchers established that the higher the tester board capacitance, the earlier the device fails. Therefore, the tester board capacitance must not only be specified, but it must also be limited to some maximum value. The MIL standard does not specify this parameter; therefore, testers that do not conform to these limits would then be producing questionable data.

A fourth published work studied the transient behavior of protection devices during HBM stress and the interaction between the HBM tester and the ESD protection devices.¹² Correlation (HBM to HBM) problems resulted because of the complex interaction between the protection devices and the testers. They then compared HBM and TLP data from two different testers using the same 4th-order LEM extractions. They indicated that the TLP data provided better correlation between the experiment and the simulation. Hence, they concluded that the HBM failure thresholds for several devices using several testers were highly influenced and dominated by the tester board capacitance.

The fifth group investigated the impact of the actual increase in the effective tester-board capacitance in the same tester type using two different test boards (motherboards) and the 500-W load.¹⁷ The effect of the increase was tested because future simulators designed to test products beyond 1024 pins will likely have built-in increased stray tester parasitics, including the tester board capacitances and the associated tester relay of the switching matrix.¹² Note here that the parasitics for the socket adapter board, the shunt capacitor across the HBM resistor, and the series inductance of the discharge path all remained the same for this experiment. One of the motherboards measured 14.5 nanoseconds for the 500-W rise time, which met the older 1991 ESDA/ANSI standard specification range of 5–20 nanoseconds. The second motherboard was modified by adding capacitance to meet the suggested increased higher-pin-count-tester specification of 5–25 nanoseconds (see Figure 3). The measured rise time was 24.6 nanoseconds, a 69% increase in the measured value (14.5 nanoseconds) of the first motherboard. This increase is quite significant.

 

Figure 3. The addition of copper foil to motherboard; connecting a current probe for a complex SMT socket.

The authors demonstrated that for the 500-W-load measurement, the increased stray capacitance affects the rise time by slowing it down (increased value). Hence, the slower the open-load measured rise time, the larger the tester board capacitance. It is clear then that because the tester board capacitance is shunted during the short test, only the 500-W open-load test can provide extracted value for the capacitance.

To further emphasize the importance of tester board capacitance and the need for the 500-W measurement, these authors focused on the buildup of the voltage across two pins as the HBM pulse is applied.^{11,12,15,18,19} They tracked the voltage buildup simultaneously (from the same HBM pulse) across the parallel parasitic tester-board capacitance. This tester-board capacitance voltage is subsequently discharged into the same protection circuit. This additional pulse from the tester board capacitance causes more stress to the protection circuit. It has been shown by some of these same researchers that this additional pulse can cause added failures at lower voltages than would have occurred if the tester-board capacitance had been lower. It follows also that by not specifying the 500-W-load test, the data from using such a tester is questionable, and, therefore, the standard becomes highly suspect. The MIL standard does not specify the use of the 500-W-load test.

The (I_p Zero Ohm)/(I_p 500-W) Current Ratio

A consequence of the 500-W open-load test is the ratio calculation for I_p0 and I_p500, which is not addressed in the MIL standard but is specified in the ESDA standard. This peak current is defined for 1000 V rather than 2000 V, and further specifies that I_p500 must not be less than 63% of I_p0 for the same stress level, i.e., I_p500/I_p0 > 63%.

In work published in 1996, the authors were able to show that if the ratio is specified and limits are set, then the limits reflect the corresponding limits to the total system tester-board capacitance, which should be below 46 pF.¹⁸ Noting that the MIL standard does not address this issue, both parameters are unspecified and can result in noncorrelatable data between testers with the lower capacitance and those with allowable higher tester-board capacitance.

Device Cool-Down Time

The two standards differ in their specification of cool-down time between pulses. The MIL standard allows 1 second (1000 milliseconds), whereas the ESDA standard specifies a reduced time of 300 milliseconds. This may appear to be significant, but published data show that there were no changes in the device behavior (i.e., failure threshold, silicon heating, and cumulative damage) between 10-millisecond and up to 1-second intervals between pulses.¹⁸ The shorter time between pulses simply allows for faster throughput in stress testing the devices.

No-Connect (Nonwired) Pins

The MIL standard 883E-Method 3015.7, 1989, specifically states that the no-connect pins are not to be tested. However, the ESDA HBM 2001 standard requires that all pins on a device be tested, even the pins listed as no-connects.

The reasoning is that some pins that are labeled no-connect could actually be connected. Even though a simple short test could verify this condition, there are other reasons for wanting to stress the pin. Published data show that no-connect pins—even though they are not stressed—could lead to arcing within the insulative packages.²⁰ Discharging through the package can occur from one no-connect pin to an adjacent wired pin. Their explanation is that the package material around the no-connect pin becomes charged, and the sudden spark discharge currents will flow into the adjacent wired pins, which could cause ESD failure if the combined current is high enough. So, adjacent pins are more susceptible, even though the authors showed that the failure mode was always the same. 

Conclusion

It was clearly shown that the Rosetta Stone analysis can provide meaningful comparison between documents from different organizations—documents that were developed to provide the procedure for ESD stress testing of the same type. Even though the many differences were not discussed, specific attention was paid to the ones that were the most significant. These included differences such as the waveform peak current, the rise time, the decay time, the short test, and the 500-W open-load test. The 500-W-load resistor test was shown to be the most significant difference. Because it directly measures the tester board parasitic capacitance, it therefore has the largest impact on the failure thresholds of devices being stress tested.

This review article also clearly demonstrated that if certain parameters are not specified in the document, then the test results could be questionable. Although pin-combination testing is quite important, it was not addressed here for several reasons. Currently, the ESDA working group is addressing these issues in the HBM standard, with the goal of upgrading the existing HBM standard.

Many standards organizations have developed standard procedures for testing devices to the HBM ESD event. However, a recent popular saying applies here: "all ESD testing standards are not created equal," and, therefore, you must have a thorough understanding of what is in a standard before it is quoted and used for stress testing. The ESDA HBM standard has been improved, but the HBM MIL standard still has major deficiencies. In its 1989 revised format, the MIL standard is not recommended for HBM sensitivity testing to qualify product.

References

1. Leo G Henry, "All Types of ESD Testing Are Not Created Equal—Part 1," Compliance Engineering 20, no. 2 (2003): 22–27.

2. ESD STM-5.1-HBM, 2001, "Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing, Human Body Model—Component Level," ESD Association, Rome, NY.

3. ESD STM-5.2-MM, 2001, "Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing, Machine Model—Component Level," ESD Association, Rome, NY.

4. ESD STM-5.3.1-CDM, 1999, "Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing, Charged Device Model—Component Level," ESD Association, Rome, NY.

5. AEC–Q101-001, Rev-B, July 2000, "Human Body Model (HBM) Electrostatic Discharge (ESD) Test-Discrete Component," Automotive Electronics Council, Component Technical Committee, July 2000.

6. EIA/JESD 22-114B, "Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)," 2000. JEDEC Solid State Technology Association, Arlington VA.

7. J/RJC-Std. ED-4701-1-C111A, 1994, "The HBM Sensitivity Test," Reliability Center for Electronic Components for Japan, Tokyo.

8. MIL-883E-Method 3015.7, "Electrostatic Discharge Sensitivity Classification—The Human Body Model, U.S. Military Standard, 1989.

9. Leo G Henry, "Who or What Is Rosetta Stone?" ESD Threshold 9, no. 2, (2003): 9.

10. ESDA DSP 5.5 TLP, 2003, "Draft Standard Practice for Electrostatic Discharge (ESD) Sensitivity Testing, Transmission Line Pulse—Component Level," ESD Association, Rome, NY.

11. K Verhaege et al., "Analysis of HBM ESD Testers and Specifications using the 4th Order Lumped Element Model" in Proceedings of the EOS/ESD Symposium (Lake Buena Vista, FL: ESD Association, 1993), 129.

12. C Russ, H Gieser, and K Verhaege, "ESD Protection Elements During HBM Stress Tests—Further Numerical and Experimental Results," in Proceedings of the EOS/ESD Symposium (Las Vegas: ESD Association, 1994), 96.

13. Bandwidth and Sampling Rate in Digitizing Oscilloscopes, Product Notice #54720A-1, Hewlett Packard Publication, 1992.

14. Leo G Henry, "AMD Internal Technical Report on ESD Testing, Reliability Engineering," AMD, Sunnyvale, CA, 1997.

15. L van Roozandaal et al., "Standard ESD Testing of Integrated Circuits," in Proceedings of the EOS/ESD Symposium (Lake Buena Vista, FL: ESD Association, 1990), 119.

16. A Amerasekera and J Kerweij, "ESD in Integrated Circuits," Quality and Reliability International 8, (1992): 259–272.

17. F Khosropour, Leo G Henry, and I Morgan, "Comparison of Failure for HBM ESD Testers Meeting ANSI/ESDA S-5.1 or the New ESDA Standard Test Method and JEDEC Standard," in Proceedings of the 24th ISTFA (Dallas: Electronic Device Failure Analysis Society, 1998), 337.

18. K Verhaege et al., "Recommendations to Further Improvements of HBM ESD Component Level Test Specifications," in Proceedings of the EOS/ESD Symposium (Orlando, FL: ESD Association, 1996), 40.

19. K Verhaege, "Component Level ESD Testing," Microelectronics Reliability 38, no. 1, (1998): 115–128.

20. M Matsumoto, M Ura, K Miyamoto, "New Failure Mechanism Due to Non-Wired Pin ESD Stressing," in Proceedings of the EOS/ESD Symposium (Las Vegas: ESD Association, 1994), 90.

Leo G. Henry is chief engineer for ESD-EMI-TLP Engineering Consultants (Fremont, CA). He can be reached at 510-708-5252 or leogesd@ieee.org.