In component-level ESD testing, selection of the right type of testing is critical to determining the type of ESD failure.

 

Leo G. Henry

This new column will explore ESD issues ranging from testing methods to ESD control. The author is Leo G. Henry, an independent ESD consultant. He has worked in the electronics industry for 19 years, with a specialty in ESD. He worked as a senior scientist and senior ESD consulting engineer at Ion in Berkeley, CA. Prior to joining Ion, he was an ESD/TLP consultant to BEI Inc. in Boulder City, NV. He has worked in the areas of ESD, EOS, latch-up, and reliability, including IC ESD testing and failure analysis. Since 1992, he has been teaching the basics of EOS and ESD testing, with a focus on the difference between EOS and ESD failures.

The concept of electrostatic discharge (ESD) testing is so old, so traditional, and probably so mainstream that it may have taken on a broader meaning than originally intended. In fact, if we are not very careful to follow up with specifics (and depending on who you are talking to), the uttering of those two words ESD testing can be interpreted in several ways. Here is a list of the different types of ESD testing that can be performed on products:

• Component-level device (integrated circuit) ESD testing.

• System-level ESD testing for equipment.

• ESD testing of materials.

• Mass storage/magneto-resistive (MR) head ESD testing.

• Printed circuit board (PCB)-level ESD testing.

• Strip-level ESD testing.

• Transmission-line pulse (TLP) ESD testing.

With the exception of TLP testing, all of these relate to an ESD model or event being used to test the product. TLP ESD testing, however, relates to the type of testing and can be used to replicate or simulate some of the other types of ESD testing. It is used in design and engineering development, but it is not yet used as a qualification tool.

ESD testing is done to weed out any ESD-susceptible devices and to maintain the quality of the products being shipped.^1,2 Equally important is the need to be able to differentiate between the electrical overstress (EOS) failure signature and the ESD failure signature of the failed products returning from the factory and the field.³

Some of the earliest published articles recognized that ESD testing must be done to reconfirm failures attributed to the various forms of ESD.^4,5 ESD testing uses four established and traditional ESD events called the human body model (HBM), the machine model (MM), the charged device model (CDM), and the human metal model (HMM).^{1, 6, 7}

In part 1 of this article, component-level ESD testing will be discussed in detail. The other types will be addressed at length in part 2 of the series.

Component-Level ESD Testing

Testing the susceptibility of a component, device, or IC to an ESD event is done using one or more of the three established component-level ESD models: HBM, MM, or CDM. Standards do exist for these three models, and a "Rosetta stone" analysis and review will be done in a future issue.^8–10

HBM and MM Testing. For the HBM ESD event, the test attempts to simulate what happens when a human becomes charged (through motion, walking, etc.), and then discharges by touching the conductive leads of a device. This device, at the time of the discharge, is assumed to be at a lower potential. The worst-case scenario is when one of the leads of the device is actually grounded. For example, this would be the case when a device is sitting on a grounded workbench surface with one or more of the leads facing downward.

Figure 1. The HBM ESD equivalent circuit. Current source for the HBM event.

For the MM ESD event, the ESD test is modeled after a charged conductive body or machine coming into direct contact with the conductive leads of the device. Again, one or more leads of the device is assumed to be at a lower potential for the discharge to occur.

The HBM event (see Figure 1) and the MM event (see Figure 2) have many differences. The two main differences are key: the MM charging capacitor is larger (200 pF) compared with 100 pF used for HBM, and the HBM requires a 1500-(omega) dc resistance in the discharging circuit. Although dc resistance for the MM is zero, there is some source impedance associated with the discharge because of the direct metal-to-metal contact.

Figure 2. The MM ESD equivalent circuit. Voltage source for the MM event.

Pin Combination. ESD testing using the HBM and MM events requires pin-to-pin combination stressing, which takes the form of testing the input/output (I/O) pins to V_ss, testing the same I/O pins to the V_dd pins, testing the V_dd pins to the V_ss pins, testing I/O to I/O, etc., until a predetermined set of combinations have been completed. This type of testing dates back to 1979 and is still used today.¹¹ The goal of this type of testing is to determine which path is the critical current path in the IC that leads to device damage.^12,13

Typical sample sizes are 15 (5 voltage levels X 3 devices) for HBM and 9 (3 voltage levels X 3 devices) for MM. This sample size assumes that fresh devices (minimum of 3) are used for each voltage level to avoid step-stress hardening and cumulative damage in the device.¹⁴ Additional devices are required if the minimum number of pin combinations is considered. Multiple pulses (both polarities) are applied to each pin, depending on the ESD model used. A time interval of 300 milliseconds to 1 second is applied between each pulse to minimize the accumulated heating effect. Completing both parametric and functional testing is essential before and after each stress test. Any single pin failure represents total device failure at that voltage level.

Figure 3. (a) Field-induced mode—CDM. (b) The CDM ESD equivalent circuit for the nonsocketed direct-charge mode.

Both the HBM and the MM stress tests are described using standard test methods.^8,9 These methods in general provide a definitive procedure for the identification, measurement, and evaluation of one or more qualities, characteristics, or properties of the product or process that yields a reproducible test result.

CDM Testing. Because the process and the physics of the CDM process are quite different from those of the HBM and MM events, there is no pin-combination testing for CDM. The sample size is simply 6 levels X 3 per level for a total of 18 devices. The HBM and MM processes involve a flow of ESD current into the device from an external pulse source, but the CDM current flows at discharge (from a charge buildup in the device and the package) through a pin that becomes grounded or set to a lower potential.¹²

For the CDM ESD event, the test is meant to simulate discharge from a charged IC through one of its pins into the low-impedance ground (see Figure 3). Hence, the testing for CDM susceptibility simply involves charging the whole device, then discharging through a pin that has been grounded.

The peak current (excluding the time dependency of the full waveform) into the device varies with the package type and the parasitic inductance in the device as follows:

I_p ≅ V X √C/L,

where V is the charging voltage, L is the inductance in the current, and C is the capacitance. At 1000 V charging, if the device C = 1 pF and L = 1 nH, then the peak current, I_p = 14 A.¹²

There are two CDM testing modes that produce the same failure signature, the field-induced charge mode (FICM). For the FICM test, the device lies dead-bug (pins facing up) on the charging table or field plate (see Figure 3a). Using vacuum, an insulated, packaged device is in intimate mechanical contact with a charging plate during the charging process. For the discharge, the pins are contacted via a grounded probe pin mounted on a robotic arm. This is referred to as an air-discharge nonsocketed CDM method.

The direct-contact charge mode (DCCM) uses a large series resistor (megohms) to provide a slow, nondamaging charge to the substrate of the device (see Figure 3b). The procedure for both modes is the same. The failure signatures are the same for both CDM modes, but are different from those for HBM and MM.¹⁴

Figure 4. SDM—socketed-device simulator setup. (Courtesy ESDA WG-5.3.2 Ref.-15.)

SDM Testing. For the third mode, designated the socketed device model (SDM), the device sits in a socket, resulting in the device, the socket, the equipment-test fixture board, the high-voltage relays, the ground relays, the pogo pins, and other parts of the test simulator being charged and discharged during the test (see Figure 4). The resulting discharge currents, into the device, therefore, are not just from the charged device. They also result from the parasitic capacitance and inductive elements in the socket and the simulator distributive network.¹⁵

It could be argued that this mode is a worst-case real-world failure, but it is not CDM in the strictest sense of the definition. ESDA Working Group 5.3.2 designated this mode as socket device model. It could arguably have also been called the simulator socket-device model.¹⁶ Even though SDM has been shown to eliminate the weak pins, the failure thresholds for SDM do not correlate to those of the CDM failure levels. However, both methods produce similar-type failure signatures, and in the same internal location of the device.

The procedure for all three CDM-like testing modes is the same. Perform full static and dynamic testing (according to the specified component data-sheet parameters) prior to and following ESD stress testing. Test a minimum of three samples. Charge the whole device through the substrate, then discharge each pin individually. Discharge three positive and three negative pulses from each pin. Repeat this step until all pins from the three components have been stressed and passed at that level.

To avoid possible stress hardening and cumulative damage in the IC, three new devices are stressed at each voltage level.¹⁷ For CDM, there are six stress levels from 125 to 2000 V, with 125-V increments as a minimum to avoid overlapping the current associated with each voltage level. For SDM, there are five stress levels from 250 up to 1250 V with 250-V intervals.

The classifications for field-induced mode (FIM) and DCCM are the same, but there is no classification for SDM because the latter depends on the procedure provided in a standard-practice document. Standard-practice documents do not require classification of products. Existing testers employing this SDM method cannot differentiate between package types. The total capacitance and inductance of the SDM tester discharge path is so large that it swamps out any difference between the package types. This was first reported by Avery for what was then called a CDM tester built in the 1980s.¹⁸ It is the most compelling reason it is necessary to differentiate between CDM and SDM.

The SDM event and test method are described by a standard-practice document, which provides a procedure for performing one or more operations or functions that may or may not yield a reproducible test result.¹⁶

System-Level ESD Testing

Testing the immunity of a system to ESD involves using a model that represents a charged human holding a metallic object and using the metal tip of the object to contact the frame (exterior) of a piece of equipment. This is sometimes referred to as the human metal model (HMM) for systems where the charging capacitor is 150 pF and the discharging resistor is 350 Ω, a value considerably reduced from the 1500-Ω component-level HBM value (see Figure 5). The event is also referred to as the hand metal model. When such an event impinges upon a piece of equipment, the discharge is usually indirectly coupled to the operating IC. In this mode, the equipment is prone to malfunction or lock up at voltage levels well below the levels likely to cause damage to the ICs located on a board in the system.

Figure 5. HMM system-level ESD tester circuit.

IEC-1000-4-2 (formerly IEC-801-2), the existing system-level ESD standard, was developed by the International Electrotechnical Commission (IEC).¹⁹ The 4-2 designation covers the electrostatic discharge requirements. Over the years, this standard has been used to test more than just automatic test equipment (ATE). A future column will compare and discuss various improvements to more closely simulate real-world threats and show the modifications to the original test method used to test those systems.

Mass Storage/MR Head ESD Testing

The mass storage industry presents many products to be tested at levels as diverse as those for the IC industry. These products are the very thin film recording-head structures (inductive and magnetoresistive) found in disk drives. One of the first publications of the ESD testing of these devices occurred in 1995. These researchers used the HBM, MM, and CDM ESD transients to test these products.²⁰ These MR heads were found to be much more sensitive to ESD than ICs. Melting of the resistive sensor occurred at a much lower failure voltage, current, or energy. Although many papers describe different procedures used for ESD testing these MR products, no standardized procedures presently address the testing of these specific device types. However, the Santa Clara, CA–based IDEMA WG has been working toward providing these testing guidelines. ²¹

Board-Level ESD Testing

The earliest published confirmations that ESD happens on printed circuit boards (PCBs) or printed wiring boards (PWBs) were reported by several researchers.¹¹ They showed that board-mounted ICs that were robust to ESD at the component level could be damaged by ESD at the board level. The individual components mounted on the board showed failures with a definite ESD-like signature, but they were more severe than the damages caused by HBM, MM, or CDM.

Detailed testing data showed that the board-mounted ICs were damaged by the discharge current that flows when an inductively charged PCB is grounded via one of its input connectors. Because the majority of the charge is stored in the capacitance of the PWB, the concept of the charged board model (CBM) was born and first reported in 1985.²² This discharge mechanism is called the CBM transient. It is analogous to the CDM transient. Testing to the CBM event is similar to testing to the CDM event. Because there were no standards to follow, CBM stress-testing methods and procedures have been developed by in-house design and product groups. No specific standardized procedures yet exist for testing these boards.

ESD Testing of Materials

This testing must be performed because materials are a part of the ESD control cycle or circle. Halperin and others addressed the causes of static control rather than measuring its effects, by focusing on the materials that produced the static.²³ They addressed the measurement of these materials mainly using static decay-time tests. In later years, the emphasis shifted to more-meaningful and dependable resistance testing. Standards for ESD control do exist for materials testing, but the scope of this article does not allow for a more detailed discussion.²⁴

Strip-Level ESD Testing

The earliest report of what is termed strip-level ESD testing was presented at the 2002 EOS/ESD Symposium by Olney et al.²⁵ Some devices are manufactured on a lead-frame strip before they are separated into individual pieces. The devices, while on the lead-frame strip, have been found to exhibit failures at a voltage lower than that of the individual components. The failures were duplicated by charging the lead-frame strip and then by discharging the strip through one of the pins of the device. This was referred to by the authors as the charge strip model (CSM).

It was found that devices that are immune to CDM are susceptible to CSM. The CSM damages were both ESD-like (silicon junction damage) and EOS-like (metal melting), depending on the package type. There is no existing standard for strip-level ESD testing, but the apparent importance of this testing is such that it warrants a more-detailed discussion in a future article.

Transmission-Line Pulse Testing

TLP is an engineering characterization tool or a development tool. It can be shown to represent or simulate most, if not all, of the previously mentioned ESD events and models. TLP testing of ICs first appeared in the literature when Maloney and Khurana presented their unique approach to testing the susceptibility to ESD of the IC core's protection structures.²⁶ Their two-pin stress testing technique was similar in some ways to that of the existing test method in the HBM standard. However, the way in which the HBM test was developed limited it to a pass-or-fail test.²⁷ The data obtained from TLP stress are more useful to design and product engineers for development and design purposes. TLP uses rectangular-pulse testing (RPT) or square-pulse testing (SPT) to simulate the energy in an exponential HBM test pulse.

No standard exists for TLP testing, but the ESD Association's standards Working Group (WG 5.5) is finalizing a document on TLP testing.²⁸ This standard-practice (SP) document will be available to industry for use by this summer. The document represents the combination of the work experience of nearly 30 engineers, scientists, and researchers from at least 11 different companies. The TLP SP-5.5 document should have a broad appeal. The details of TLP testing will be addressed in part 2 of this article.

Conclusion

When a concept has been around as long as electrostatic discharge (ESD) testing, it takes on a much broader meaning than originally intended, which leads to much confusion and differing interpretations. Even those who are deeply involved in the study of ESD testing must be careful to be very specific when discussing any aspect of this topic.

As discussed above, there are many types of ESD testing, and, as the saying goes, "All devices are not created equal," and, therefore, testing must be done to differentiate between the "good, the bad, and the latent." ¹²

References

1. Leo G Henry and Michael Chaine, "Component Level ESD Challenges," in ESD Phenomena and Reliability for Microelectronics (Rome, NY: ESD Association, 2002), 27–30.

2. Paul O'Shea, "What You Need to Know About Device Testing," Evaluation Engineering, December (1997): 82.

3. Leo G Henry et al., "EOS and ESD Laboratory Simulation and Signature Analysis," in Proceedings of ISTFA, (Materials Park, OH: International Symposium for Testing and Failure Analysis, 2000), 117–126.

4. Owen J McAteer, "An Effective ESD Awareness Training Program," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1979), 79.

5. TM Madzy and LA Price II, "Module Electro-Static Discharge Simulator" in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1979), 36.

6. G Branberg, "Electrostatic Discharge of CMOS Logic," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1979), 55.

7. WM King, "Dynamic Waveform Characteristics of Personnel Electrostatic Discharge," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1979), 78.

8. ESD STM-5.1-HBM, 1999, "Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing, Human Body Model—Component Level," ESD Association, Rome, NY.

9. ESD STM-5.2-MM, 1996, "Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing, Machine Model—Component Level, ESD Association, Rome, NY.

10. ESD STM-5.3.1-CDM, 1999, "Standard Test Method for Electrostatic Discharge (ESD) Sensitivity Testing, Charged Device Model (CDM)—Component Level, ESD Association, Rome, NY.

11. EJ McMahon, TN Bhai, and T Oishi, "Proposed MIL STD and MIL HNBK for an ESD Control Program," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1979), 27.

12. Leo G Henry, "ESD Testing of Integrated Circuits," Future Circuits International 3, (1998): 249.

13. K Verhaege, "Component Level ESD Testing," Microelectronics Reliability Journal 38, no. 1 (1998): 115–128.

14. L Avery, "Beyond MIL HBM Testing: How to Evaluate the Real Reliability of Protection Structures," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1991), 120.

15. M Chaine et al., "The SDM Test Method: Past, Present and Future," Compliance Engineering 18, no. 7 (2001): 36–43.

16. ESD SP5.3.2-SDM, 2002, "Standard Practice for Electrostatic Discharge (ESD) Sensitivity Testing—Socketed Device Model (SDM)—Component Level," ESD Association, Rome, NY.

17. Leo G Henry et al., "ESD Lab Simulations and Signature Analysis of a CMOS Programmable Logic Product," Microelectronics Reliability Journal 38, (1998): 1715–1721.

18. L Avery, "CDM Testing: Trying to Duplicate Reality," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1987), 88.

19. IEC 1000-4-2, "Electro-Static Discharge Requirements for Immunity," System Level Standard, International Electrotechnical Commission, 1991.

20. AJ Wallash and TS Hughbanks, "ESD Failure Mechanisms of Inductive and Magnetoresistive Recording Heads," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1995), 322.

21. "New ESD Standards Expected to Fill Gap for Disk Drive Industry," in Newsline, Compliance Engineering 17, no. 5 (2000): 14–18.

22. RN Shaw and RD Enoch, "An Experimental Investigation of ESD-Induced Damages to ICs on PCBs," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association,1986): 132.

23. SA Halperin, "Static Control Using Topical Antistats," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1979), 13.

24. ANSI/ESDA Standard S20.20, "ESD Control Program for the Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices), ESD Association, Rome, NY, 1999.

25. A Olney et al., " A New ESD Model: The Charged Strip Model," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 2002), 163.

26. TJ Maloney and N Khurana, "Transmission Line Pulsing Techniques for Circuit Modeling," in Proceedings of the EOS/ESD Symposium (Rome, NY: ESD Association, 1985), 49.

27. LG Henry et al., "TLP Testing of the ESD Protection Structure of ICs—A Failure Analysis Perspective," in Proceedings of ISTFA, (Materials Park, OH: International Symposium for Testing and Failure Analysis, 2000), 203.

28. ESD SP5.5-TLP, 2002, "Standard Practice for Electrostatic Discharge (ESD) Sensitivity Testing, Transmission Line Pulse (TLP) Testing—Component Level," ESD Association, Rome, NY.

Leo G. Henry is chief engineer for ESD-EMI-TLP Consultants (Fremont, CA). He can be reached at 510-708-5252 or leogesd@ieee.org.