For boards containing circuits that interface with outside-plant tip/ring pairs, one such challenge is maintaining immunity to lightning strikes and unintentional power-line contact (power cross). This article explores this challenge as it relates to PCB layout. Through experimentation and analysis, this article provides designers with data to use as a tool when laying out circuits that will interface with outside plant wiring.

With product size decreased and component density increased, PCB real estate quickly becomes limited. Designers must decide on board dimensions, component placement, and layer count: factors that can affect both product performance and cost. This task is further complicated when the product in question contains circuits that could be exposed to external lightning and power-cross events.

Component and trace spacings are critical to avoid arcing during high-voltage transients. Trace width is critical to avoid blown traces during high-current transients. Although designers want to design products that are immune to such events, they do not want to overburden a design with placement and routing constraints that are excessive. To ensure optimum efficiency during board layout, designers must have a thorough understanding of the properties PCB traces exhibit during transient events. This article discusses the results of an experiment intended to quantify the physical characteristics of a multilayer PCB during high voltage and high current transients.

The findings were obtained by performing the following tests on multiple PCB test samples: 10 x 1000-microsecond, 1000-V, 100-A surge; 2 x 10-microsecond, 2500-V, 500-A surge, and one 600-V, 60-A power-cross transient. These events were taken from Telcordia's GR-1089-CORE.¹ They represent the worst-case energy dissipation that a PCB can experience during formal testing and be expected to survive.

Although not required by GR-1089-CORE, it is advantageous for an overcurrent protection device to interrupt the 600-V, 60-A power-cross transient rather than the PCB traces. Interrupting the transient allows for repair of the product not only in the lab but also once installed in the field, which eliminates the cost of a new circuit pack.

The requirements detailed in GR-1089-CORE were developed around the performance characteristics of a standard 3-mil carbon block. The carbon block is considered to have the greatest let-through energy of all of the commonly used primary protectors in the telecommunications industry. Test samples were evaluated under various conditions to simulate not only ideal-case scenarios, but also real-world conditions a board might experience due to manufacturing issues and years of service in the field.

The experiment had five objectives, which are discussed below:

For this experiment, a four-layer PCB was designed by Underwriters Laboratories (UL) and fabricated by an outside board vendor. A four-layer board was chosen because it allowed for data collection on the surface as well as on the internal layers. Two batches of boards were fabricated, one with solder mask and one without. Each batch used the same trace layout. Figures 1–4 show a view of the trace layout for each layer. The photos show each type of board used. The physical specifications for the boards were as follows:

To quantify the dielectric properties of the spaced traces on the PCBs, a calibrated dielectric withstand tester was used to apply a dc potential (maximum 5000 V) between the traces (see Figure 5). The following layers were evaluated:

To quantify the current-carrying properties of the various traces, the boards were subjected to the 2500-V, 500-A, 2 c 10-microsecond lightning surge, the 1000-V, 100-A, 10 x 1000-microsecond lightning surge, and the 600-V, 60-A power-cross transient detailed in GR-1089-CORE. Tables I–IV and Figures 6–8 present the data gathered from the experiment.

A KeyTek (Lowell, MA) ECAT surge generator was used to produce the lightning waveforms, and a UL-built power-cross generator was used to produce the power-cross transient. Lightning waveforms were monitored using a calibrated digital oscilloscope (see Figure 9).

Figure 9. Lightning waveforms are monitored using a calibrated digital oscilloscope.

Power-cross values were monitored using calibrated digital meters (see Figure 10). The following layers were evaluated: surface layer with no solder mask, surface layer with solder mask, and internal layer.

The experiment revealed minimum trace-to-trace spacing required on external and internal layers of a PCB. The minimum spacings to ensure no dielectric breakdown during the application of the 2500-V, 500-A, 2 x 10-microsecond first-level surge defined in GR-1089-CORE are as follows:

To ensure no dielectric breakdown during the application of the 1000-V, 100-A, 10 x 1000-microsecond first-level surge, the minimum trace-to-trace spacings are as follows:

The experiment also revealed the minimum trace width required on external and internal layers of a PCB. To ensure a trace does not become an open circuit during the application of the 2500-V, 500-A, 2 x 10-microsecond first-level surge defined in GR-1089-CORE, the following trace widths are required, depending on the layer:

To ensure a trace does not become an open circuit during the application of the 1000-V, 100-A, 10 x 1000-microsecond first-level surge, the following minimum trace widths are required on external and internal layers of a PCB:

A minimum trace width is required on external and internal layers of a PCB. This minimum trace width ensures the trace's fuse characteristics are greater than that of a Bussman Type MDQ 1-6/10A fuse when subjected to the 600-V, 60-A second-level power-cross transient detailed in GR-1089-CORE. The following minimum widths are required:

Several observations were made from the data. Surface-layer traces with no solder mask have a lower dielectric breakdown voltage than surface-layer traces with solder mask. Internal-layer traces have a higher dielectric breakdown voltage than surface-layer traces. Surface-layer impurities lower the dielectric breakdown voltage, and surface-layer traces with no solder mask have a lower current-carrying capacity than surface-layer traces with solder mask. Finally, internal-layer traces have a lower current-carrying capacity than surface layers.

The information presented in this article is not meant to be a rule book for designers to use when laying out circuits exposed to external transients. Rather, it should be used as one of many tools to successfully design a circuit that is immune to surge and power-cross transients.

Although this experiment concentrated on the impact that both high voltage and high current transients have on PCB traces, these data can be used to aid in component selection, component placement, and connector pin assignments. Surge suppression devices and overcurrent protection may help reduce the trace spacing and width constraints presented in this article. By coordinating these devices with the data provided in this article, arcing and blown traces should be avoided during formal testing and, hopefully, during field service as well.