The Return Path: Impedance Control on Printed Circuit
D. Kimmel and Daryl D. Gerke
the impedance along the entire signal path is increasingly
important as high-speed digital designs become more common.
term signal integrity (SI) is getting increased
visibility in the world of EMC. In fact, the IEEE EMC
Society has adopted signal integrity as one of its 10
technical committees. Spearheaded by Mark Montrose (a
director of the society), this committee is chaired by
Charles Grasso. Activity in this area should continue
to increase in the coming years as signal speeds push
well into the gigahertz range.
encompasses any signal type, whether it is high-speed
digital, low-level analog, or radio frequency (RF), but
it is high-speed design that puts signal integrity into
the EMC vocabularyand much of an EMC engineer's focus
involves controlling high-speed-signal reflections. Much
has been written about reflections and termination types,
so these topics are only touched on here. See the sidebar
"Recommended Reading" for more in-depth information. This
article focuses on the most common cause of reflections:
failure to control the impedance along the entire signal
path and, no less important, the return path.
Integrity and EMC
would signal integrity be considered an aspect of EMC?
To answer this question, it is important to examine EMC
in a broader sense. Regulatory aspects are certainly important
to manufacturers, but end-users take a systems viewpoint
of EMC: Does the equipment work as intended? EMC at the
circuit board levelinterference with adjacent signalsis
at the other extreme. This is known as signal integrity.
adds a new dimension to EMC. A signal that degrades along
the signal path may experience no interference with members
outside of its own path. This degradation is of no consequence
in regulatory requirements, but it is critical to SI engineers.
On the whole, SI and EMC design techniques have a significant
overlap: a board designed well from an SI standpoint is
a major step toward good EMC design.
levels are much different, however. SI generally works
with millivolts and milliamps, whereas EMC deals with
microvolts and microamps for emissions and kilovolts and
amps for immunity.
first problem in high-speed SI is the need to minimize
signal reflections. These reflections are a significant
concern when the propagation delay along the signal path
becomes comparable to the signal rise time. In the ideal
case, where the characteristic impedance (Z0)
of the signal path is constant along the way and the load
is equal to Z0,
the signal is absorbed at the load without reflections.
notable alternative to this case is when the termination
is at the source rather than at the load. One reflection
is tolerated, with the return reflection being absorbed
at the source. (This technique was a favorite of Seymore
Cray of Cray Research). Failure to terminate properly
results in reflections and degraded signals.13
is SI such a pressing issue now? The answer is, simply,
speed. Impedance control has been an issue for RF experts
for the better part of a century and for high-speed data
and super-computer experts (e.g., emitter-coupled logic
[ECL] users) for more than a quarter century. It is only
recently, however, that high speeds have shown up in everyday
design, which has mandated distributed circuit-design
does impedance control become necessary? If a designer
is concerned about the speed of signal propagation on
a circuit board, the board is probably a candidate for
impedance control. More quantitatively, impedance control
becomes an issue when the rise time of a signal path approaches
the round-trip propagation time along a signal path. On
a typical circuit board, where the speed of light (and
signal propagation speed) is approximately 6 in./ns, the
critical length is:
(in.) = 3 tr
length (cm) = 8 tr
I indicates the approximate onset of such problems. The
most commonly observed result of unterminated lines is
a damped ring wave, caused by a combination of a high-impedance
receiver and a low-impedance driver. Reflections can occur
at either end (and that means that the termination can
be placed at either end).
Gallium arsenide (GaAs).
Emitter-coupled logic (ECL).
I. Approximate onset of impedance-control problems.
lengths shown in Table I apply to digital circuits. In
digital circuits, some ringing and overshoot is tolerable.
It is important to remember, however, that any ringing
increases crosstalk and emissions, so even shorter lengths
may be mandated. It is also important to consider the
actual rise time, which could be much faster than that
specified in the data sheet.
ideal situation is one in which the signal stays on a
single layer and runs over a continuous return path (either
a ground plane or a voltage plane). Note that the preferred
return path is the nearest plane, whether it is a ground
or a voltage plane, because it is the minimum-energy path.
Although this ideal setup is difficult to achieve and
not perfect, it is still the best.
1 shows a common scenario. The signal starts from
the driver, runs along the voltage plane to a via, drops
down to the ground plane and continues on the next via,
then comes back up another via to the voltage plane and
finally to the load. The return current follows the lowest
energy path (generally the smallest loop area) back to
the source. Ordinarily, this would be the portion of the
reference plane immediately under the signal trace. But
if this path is blocked, the return current diverts to
the smallest loop path, usually the nearest decoupling
capacitors (decap), creating a huge impedance discontinuity.
Figure 1, the return current starts along the voltage
plane (immediately under the signal trace), then encounters
the first discontinuity where it must jump to the ground
plane. The interlayer capacitance in the immediate proximity
of the via returns the highest-frequency currents (say,
1 GHz), but the intermediate frequency currents (say,
200 MHz) go through the nearest decap. The return current
continues along the ground plane (again immediately underneath
the signal trace) until it encounters the next via, where
the current has to jump back to the voltage plane and,
again, diverts to the nearest decap.
farther the decap, the greater the discontinuity. For
example, if a sniffer probe finds a very noisy decap in
an unexpected location on a high-speed board, the decap
is probably forming the return path for a high-speed clock
line. This is only one of a number of discontinuities
that can occur. Here is a sampling of problems, along
with some possible remedies:
trace passes through a via, switching reference planes
in the process (as in the case cited above). Avoid
switching reference planes for critical signals (especially
clocks and buses) wherever possible. If planes must
be switched, insert an adjacent via (if changing from
one ground plane to another ground plane) or a small
capacitor (if changing from Vcc
trace crosses a split-plane boundary (as might be used
for multiple supply voltages and as shown in Figure
2). Avoid this case, if possible, by routing
along the continuous ground plane. Otherwise, place
a small decap (0.001 µF is sufficient) across the
trace passes through a connector and has no adjacent
return line (the return current may be traveling on
a voltage or ground path). Place the signal trace
next to a ground or a voltage connector pin (as appropriate).
Better yet, surround the signal with a pair of ground
or voltage pins.
trace passes through a connector and switches reference
planes (e.g., from ground plane to voltage plane), regardless
of whether there is an adjacent ground trace. Avoid
this condition if at all possible; otherwise, place
decaps immediately at the connector of each board.
changes reference planes. Return currents from signal
switching low to high return to the Vcc
driver chip. Return currents from signal switching high
to low return to the ground of the driver chip. Therefore,
discontinuities exist at both ends of the path.
Place decaps near each critical driver and receiver
and at Vcc and ground pins.
goes to cable without impedance control. Use impedance-controlled
cables. If such cables cannot be used, interleave signals
with ground pins.
that a decap is never as good as a direct connection.
Inductance in the path of a capacitor is always higher
than that of a simple via, but using a capacitor is certainly
better than nothing. To maximize capacitor effectiveness,
adopt the following practices:
lead inductance of decaps to a minimum by placing a
via immediately at the solder pad.
decaps within about one-third of a rise time; otherwise,
they are ineffective.
critical signal linesespecially the clockas short
as possible. Where longer runs are necessary, be especially
careful about the discontinuities discussed earlier.
from the return-path discontinuities, a number of signal-line
discontinuities can cause problems as well. These are
listed below in approximate order of severity.
Stub or Branch. The difference between a stub and
a branch is the length (see Figure 3). A signal driving
more than one load poses a potential problem. The signal
starts down a trace (say, 50 W),
and then encounters a two-way branch. If each branch is
also 50 W, the signal sees
a 25-W load at the junction,
with attendant reflections. In principle, this discontinuity
can be eliminated by changing branch impedances at the
junction (e.g., a 50-W line
feeding two 100-W branches).
This solution is rarely feasible. If the branch is immediately
at the driver, the reflection is minimal, but this leaves
two parallel loads to feed, placing a significant load
on the driver. If the branch is at one of the loads, it
is called a stub. If the stub is short, it can be treated
as an extra capacitance. It is best to minimize these
stubs as well. Generally, it is good to keep the total
stub length at one-third of the maximum transmission line
3. Impedance discontinuities at stubs and branches.
Signal Layers. When the signal changes layers (and
also changes distance to the reference plane), Z0
changes as well. Therefore, if the reference plane is
on layer three and the signal changes from layer two to
layer one, the impedance changes as well. If the inner-layer
impedance is planned to be 50 W,
it may jump to 80 W on the
higher layer. It is possible to maintain a constant impedance
by using wider signal traces when the distance from the
signal to the reference plane is increased. However, such
a complex solution should be avoided. Similarly, signal
traces on other layers close to the controlled path also
lower the effective impedance of the path. Avoid the need
for impedance control on layers that are not directly
over a reference plane.
Coupling. Adjacent lines also lower the effective
impedance of the controlled path, but not to the extent
as in the case above. Crosstalk tends to be worse, however,
because adjacent lines are more likely to have long parallel
Via. The discontinuity here occurs when the trace
drops down through the via and picks up on the other side
of the same plane. Typically, this condition adds a little
inductance (less than 1 nH) in series. This inductance
isn't much of a problem until it reaches the gigahertz
range (provided the signal doesn't change planes). Smaller
holes reduce the inductance, so etch as little copper
as possible to minimize this effect.
Tolerances. Dielectric thickness variations can easily
result in impedance variations of 20% or even more. The
good news is that these variations do not result in discontinuities,
which tend to be more of a problem. In our experience,
such variations are not much of a problem.
Square Corner. This discontinuity is the one that
gets all the attention: A square corner in a signal trace
adds a small amount of additional capacitance. This capacitance
can be minimized by using two 45° bends instead of
one 90° bend or, more simply, by chamfering the corner
to reduce the capacitance. In actual practice, the square
corner is such a minor deviation compared with the problems
described above that it is not worth worrying aboutat
least until the capacitance is in the gigahertz range.
control is not complete without terminations. The traditional
parallel (and Thevenin equivalent) resistive termination
types are power hogs. Other terminations, including series
(or source) and ac can be used. Each has its own advantages
and disadvantages. Traditional terminations are likely
to give way to emerging nonlinear termination. Although
nonlinear terminations are not ideal for eliminating reflections,
they are more forgiving in real-world applications. They
can also be implemented on the die very close to the load,
as higher speeds mandate.
latest development is active nonlinear termination, which
has been championed by California Micro Devices (Milpitas,
CA).4 Such termination uses active complementary
metal-oxide semiconductor (CMOS) devices to provide the
necessary nonlinearity. More nonlinear-termination types
will likely be seen in the near future.
it is important to mention the difference between textbook
components, purchased components, and installed components.
The primary components used in signal integrity are resistors
and capacitors, although ferrites and wound inductors
might also be encountered. Most new designs use surface-mount
technology (SMT). Although this technology provides some
pretty good components, they still have some parasitic
inductance and capacitance in addition to that in the
circuit board traces and vias.
an approximation, the lead inductance can be assumed to
include 0.5 nH in the component itself, 1 nH of inductance
per via, and between 5 and 10 nH/in. of trace, depending
on the board makeup. Assume 12 pF of capacitance
in parallel with resistors (or even more, depending on
layout). This capacitance is often minimal compared with
other stray capacitance along the way, especially at the
troublesome is the series inductance in a capacitive path,
where impedance must be kept low. For example, a 0.01-
µF capacitor in series with 1 nH resonates at about
50 MHz. That does not make the capacitor useless above
resonance, but the impedance above that frequency is basically
that of the series inductance. The impedance becomes troublesome
above about 200 MHz. So, it is important to keep the series
inductance as low as possible. For decoupling, some effect
can be seen from interlayer capacitance between power
and ground planes above 200 MHz, but if a capacitor is
being used to maintain signal-path continuity, the capacitor
must stand on its own merits. The degradation is noticeable
as the frequency closes in on 1 GHz.
is best to keep the solder pad and the via as close to
one another as possible. It may even be possible to shave
off a nanohenry or so by placing the solder pad on the
side closest to the reference planes.
are often brought out to the decap from the power and
ground pins, which, in turn, tap into the power and ground
planes. There are arguments both for and against this
practice from an EMC standpoint. However, we strongly
discourage this solution if the focus is high-speed signal
integrity because the high path inductance becomes a significant
signal lines demand impedance control along the path.
To do this, the impedance needs to be controlled from
start to finish and it must be properly terminated. Impedance
discontinuities, especially those in the return path,
are the biggest single cause of signal reflections.
board analysis software can be helpful in finding these
problems, but following a few basic design rules greatly
W Johnson and Martin Graham, High-Speed Digital
Design, (Upper Saddle River, NJ: Prentice
Hall PTR, 1993).
This book concentrates on maintaining signal
integrity on circuit boards and cables. It is
not specifically an EMI book, but it still has
very useful information and is recommended for
all circuit and logic designers.
Montrose, Printed Circuit Board Design Techniques
for EMC Compliance, 2nd ed. (New York: IEEE
First-edition owners will find plenty of
new information and updates in this second edition,
including an in-depth treatment on printed circuit
board design. It also offers nuts-and-bolts
information and quantitative guidelines. Although
it is targeted at the technician and circuit
board designer, it also has good information
for design engineers as well.
R. Blood Jr., Motorola MECL System Design
Handbook, (Schaumburg, IL: Motorola Inc.,
Techniques for High Speed Busses," Application
note #AP-204, (Milpitas, CA: California Micro
Catherwood, "Designing for Electromagnetic Compatibility
(EMC) with HCMOS Microcontrollers," Application
note #AN1050, (Austin, TX: Motorola Inc., 2000).
IPC-D-317A, "Design Guidelines for Electronic Packaging
Utilizing High-Speed Techniques," IPC, Chicago, 1995.
IPC-2141, "Controlled Impedance Circuit Boards & High
Speed Logic Design," IPC, Chicago, 1996.
IEC 61188-1-2, "Printed Boards and Printed Board AssembliesDesign
and Use. Part 1-2: Generic RequirementsControlled Impedance,"
International Electrotechnical Commission, Geneva, 1998.
Jeffrey C Kalb, "Nonlinear Termination Techniques for
Electronic Systems," Compliance Engineering 18,
no. 6 (2001): 7481.
D. Kimmel, PE, and Daryl D. Gerke, PE, are cofounders
of the engineering consulting firm Kimmel Gerke Associates
Ltd., with offices in St. Paul, MN, and Phoenix, AZ. They
share more than 60 years in the EMC arena and publish
and lecture widely on the subject. They can be reached
at 888-EMI-GURU or at http://www.emiguru.com. They can
also be contacted by e-mail at email@example.com