The analyzed circuits with TVS (varistor and avalanche diode), the parasitic elements (cable and the connections), and the discharge generator circuit were inserted into the CAD program using a macromodel. The two-layer printed circuit board (PCB) consisted of three parallel microstrips for each layer. ESD was applied to the central strip of the top layer. The experimental results matched the simulations for each TVS analyzed.

Figure 1 shows the analyzed structure: two bundles of parallel lines in two different layers cross over the same ground plane. ESD was applied on one of the two central lines, and a suppressor was mounted at the end of the line. The other lines were terminated by arbitrary loads. Figure 2 shows two sections of the PCB: one parallel to the plane xz and one parallel to the plane yz.

Figure 1. Geometry of the analyzed structure.

 

Figure 2. Orthogonal sections (xz and yz) of the printed circuit. Dimensions are: Wd = 1.76 mm, Wu = 2.64 mm, h1 = 1 mm, h2 = 1.6 mm, t = 35 µm, εr = 4.9.

The CAD package treats the bundle of parallel lines as a macromodel, but it neglects the crosstalk between the crossing lines. To account for this, a lumped crosstalk capacitance was inserted to correspond with each numerically determined cross point.² Figure 3 shows the complete configuration in the CAD simulation, including loads, suppressors, and the ESD generator.

Figure 3. Configuration of printed circuit, connections, loads, suppressors, and ESD generators.

Figure 4 reports the ESD current waveform standardized by EN 61000-4-2.³ The waveform is characterized by a subnanosecond rise time and a value of the current of few amperes; the same figure shows the resistance-capacitance network specified by the standard as the equivalent circuit of the generator. It is evident that the circuit of Figure 4b, which would produce a zero rise time, cannot generate the waveform of Figure 4a. The actual ESD gun exhibits a series inductance (due to the return current ground cable), which is responsible for the finite rise time in the current waveform.

Figure 4. An ESD current waveform (a) and standardized ESD generator circuit (b) (R = 330 W, C = 150 pF).

Unfortunately, the commercial simulator also exhibits stray elements, which means that the actual waveform can be different—even though inside specifications—from the standardized one. For example, Figure 5 shows the voltage waveform produced by the laboratory ESD generator when a 6-kV discharge was applied to a 50-W coaxial cable.

Figure 5. Voltage pulse produced by a real ESD gun loaded by a matched 50-W coaxial cable.

To correctly reproduce the actual waveform, the network shown in Figure 6a was synthesized.⁴ The network, therefore, had to be added to the CAD as a macromodel. Figure 6b shows the pulse produced by the synthesized network. The circuit in Figure 6a can reproduce the initial part of the experimental waveform correctly, which is important for coupling because it is characterized by a high time derivative.

Figure 6. (a) Network for the simulation of the waveform of Figure 5 (C1 = 150 pF, R1 = 330 W, L1 = 90 nH, C2 = 2.5 pF, L2 = 60 nH). (b) Voltage waveform of the ESD applied to a coaxial cable (gun simulated by the circuit of [a]).

Suppressor Characterization

Figure 7 shows a schematic of the suppressed circuit mounted to protect a signal line. Ls represents the inductance of the connecting traces. The suppressor device can be modeled by the circuit shown in Figure 8. The suppressor is characterized by a series inductance Ls, a series resistance Rs, and a capacitance Cp parallel with a resistance Rp that is a nonlinear function of the applied voltage.

Figure 7. Circuit of a suppressor mounted on the lines to protect a signal line.

 

Figure 8. Circuit model of the transient voltage suppressor.

Two different situations must be analyzed: the component behavior in the presence of ESD excitation (i.e. its ability to clamp the applied transient) and the component's load on the line when the wanted transmitted signal flows. The CAD package approached the first, considering the macromodel for each device. Figure 9 illustrates the macromodel used for the varistor.

In Figure 9, L_wires is the inductance of the wires, R_bulk is the substrate resistance, and R_leak is the low-current resistance (for currents lower than 100 µA, typically), whereas R_ideal is the nonlinear resistance that accounts for the high current flowing. Finally, C is the capacitance at the clamping voltage. The values are assigned using both actual measurements and information taken from the manufacturer's data sheet. A more efficient suppressor for ESD excitation is an avalanche diode. Figure 10 shows the macromodel used for this component.

Figure 9. Macromodel for the varistor.

 

Figure 10. Macromodel for the avalanche diode.

In that figure, R_f and D_fw signify the component behavior up to the breakdown region. D_fw incorporates the junction capacitance that assumes the value at the breakdown voltage. E_bv and D_bd signify the component behavior in the breakdown region, and the capacitance in D_bd assumes a zero value. Figure 10 represents a unidirectional device.

When the discharge is not applied, the same component circuit can be simplified to predict the load effect on the desired transmitted signal. In particular, Rp can be ignored, and Cp assumes the zero bias value, which can differ from the one at the clamping voltage, especially for the diode.

The capacitance Cp can be measured at a low frequency (at which the series inductance effect can be ignored) by connecting the device directly to a resistance-inductance-capacitance (RLC) meter. The total series inductance value can be recovered by measuring the transmitting characteristics of the device-loaded line (see Figure 11). The procedure is described in the next section.

Figure 11. Simplified circuit for low-level signals.

Measurement Setup

For the ESD experiment, the discharge could not be performed directly on the PCB trace because the gun-radiated field would have coupled to the traces, which could not be modeled. The model considers an impulsive transverse electromagnetic mode (TEM) wave reaching the victim trace where the suppressor is mounted. Although this condition can be realized by connecting a coaxial cable to the PCB and performing the discharge at the beginning of the cable, it must be done inside a shielded room to avoid propagation of the gun-radiated field (see Figure 12). The PCB traces are then connected to a 1-GHz oscilloscope (Tektronix SCD 1000) to capture the structure's response to the ESD. The corresponding response time of the oscilloscope is 0.35 nanoseconds, sufficiently lower than the rise times to be measured.

Figure 12. Measurement setup.

Figure 13 shows the generator (Schaffner NSG 432) injecting the discharge at the beginning of the coaxial cable (RG 214) inside the shielded room. Figure 14 is a photograph of the analyzed PCB. A contact discharge is performed to ensure high repeatability in the produced waveform.

Figure 13. The ESD generator placed inside the shielded room.

 

Figure 14. The PCB circuit ready for analysis.

Two different instruments were used to measure the parasitic elements in a zero-bias operating condition. The capacitance Cp was measured by connecting the suppressor at the input of an RLC meter (Hewlett-Packard HP 4285A), using a low frequency (1 MHz) to avoid a series inductance effect. Further, a network analyzer (Hewlett-Packard HP 8753D) was used to measure the transmission coefficient of the line with the suppressor mounted. The component exhibits a series resonance (see Figure 11). Because the suppressor is mounted parallel to the line, a zero transmission occurs when the component resonates. Therefore, the inductance value can be recovered from the resonant frequency and the previously measured Cp. Simulating a clock signal, the network analyzer's time domain facility was used to determine the response of the loaded line to a step excitation.

Two commercial suppressor devices were considered for both the simulation and the actual measurements: a 275-V varistor and a 300-V diode. The varistor (Siemens-Matsushita S14K275) exhibited a clamping voltage of 275 V and a declared response time of 25 nanoseconds. The distance between terminals was 14 mm. The varistor is 1 cm in diameter. With the component mounted, the leads were 3 mm in length. The nonlinear resistance values were determined using the macromodel shown in Figure 9 (L_wire = 15 nH, R_bulk = 0.3 W, R_leak = 10 MW, C = 500 pF). The V-I characteristics from the manufacturer's data sheet were implemented for the nonlinear resistance.

The avalanche diode (Semitron 1.5KE300CA) exhibited a 300-V clamping voltage, peak power of 1500 W, an intrinsic response time of 1 picosecond, and a declared capacitance of 15 pF. The diode is a cylinder with a diameter of 4 mm and a length of 9 mm. With the component mounted, the leads were 3 mm in length. Referring to the macromodel in Figure 10, L_wires = 19 nH, R_f = 0.1 W, R_bulk = 0.3 W, E_bv = 300 V, capacitance in D_fw = 590 pF, and capacitance in D_bd = 0 pF.

Figure 15 shows the simulation results for the voltage at port 11 when the suppressor is inserted at port 8 of the circuit in Figure 3. The circuit in Figure 6a excites port 8, assuming an initial voltage of 6 kV for the capacitance C₁ and all other ports connected to a 50-W load. In this way, the excitation is the voltage pulse reported in Figure 6b. Figure 16 shows the experimental results obtained using a real ESD gun (according to the procedure described in the previous section) for 6-kV discharge. The darker line is related to the diode (clamping voltage 300 V) and the lighter line is related to the varistor (clamping voltage 275 V).

Figure 15. CAD simulation results.

 

Figure 16. Experimental results.

It is interesting to note that both devices work well at >5 nanoseconds after the discharge (forcing the voltages to their clamping characteristics), but that the first high peak passes completely through the device because of the parasitic elements, especially the series inductance. The peak occurring at about 17 nanoseconds is due to a double reflection of the ESD pulse at the two cable ends. At one end the reflection produced by the suppressor acts as a short circuit, and at the other end the reflection of the gun acts as an open circuit (R₁ = 330 W).

Small Signal Response. Figure 17 shows the transmission coefficients of the 50-W line loaded by the varistor and by the diode. It is evident that the devices greatly affect the signal transmission above 20 MHz. Table I reports the inductance values calculated using the resonance frequency and the capacitance measured with the RLC meter at 1 MHz.

Protection Device	Resonant Frequency (MHz)	Measured Capitance (pF)	Computed Inductance (nH)
Varistor, 275 V	72.18	332.5	14.6
Diode, 300 V	104.2	123.5	18.9
Table I. Measured values of parasitic parameters for two commercial suppressor devices.

It is critical to note that the inductance values are comparable for the two devices, whereas the capacitance values are significantly different. The series inductance, which depends mainly on the mounting techniques and device dimensions (similar in this case), can be reduced through the use of surface-mount devices. Moreover, the junction capacitance in the diode strongly depends on the chosen clamping voltage; for example, a diode of the same family as the one considered in this article, but with a clamping voltage of 6.8 V, exhibits a zero-bias capacitance of 4750 pF.

Step Excitation. Figure 18 illustrates the network analyzer's time domain with a frequency span of 1 GHz and a rise time of about 1.5 nanoseconds. The response of the two devices to this excitation is shown in Figure 19. When loading the line, the rise time is greatly increased, which could produce a malfunction in an actual circuit. The varistor produces a greater degradation of the input signal in accordance with its lower resonant frequency.

Figure 18. The time step produced by the network analyzer.

 

Figure 19. Step response of the varistor (a) and the diode (b) to the excitation graphed in Figure 18.

Conclusion

Using transient voltage suppressors on circuit ports can protect high-speed data lines from damage caused by ESD. The effects of different suppressors on ESD excitation was analyzed by an ad hoc commercial code developed in collaboration with High Design Technology (Turin, Italy). Circuits were analyzed with both a varistor and an avalanche diode using a macromodel in a commercial CAD program. The theoretical results agreed with the experimental ones.