Using Simulation Software to Fight PCB Emissions

Simulating a variety of options can minimize the trouble in identifying the source of—and the solution to—emissions problems.

Al Wexler

Once excessive emissions are detected at several frequencies, the goal is to quench these emissions. Some techniques are crude and expensive and involve the design of sealed enclosures, chokes, and ferrites to restrain the launching of common-mode currents along cables. A variety of other methods for suppressing unwanted emissions reduce them too little and too late in the process. Alternatively, system developers recognize that the problem should be addressed at the board level. But even if the problem is identified, engineers still must locate the wires that are producing the emissions. This article describes a simulation technique for identifying the nets that cause excessive emissions and signal integrity problems. Simple techniques, such as the attachment of components to drivers and receivers, can be used to suppress these emissions, but the source must first be identified.

 

Figure 1. Maximum magnetic field (Hx, Hy, and Hz) spectrum, at a height of 5 mm (50-MHz clock).

Signal integrity and emission problems should be addressed in the course of printed circuit board (PCB) layout. One method is basically a simulated sniffer-probe operation over the board. Because emissions begin at the board level, it makes practical engineering sense to clean up board-level problems before going further. Some simulation software provides default behavioral models within the software. Such models are usually adequate for finding the nets causing the emissions. Detailed libraries, therefore, are not essential to the process of identifying the source of emissions (see Figure 1).

The Method

 

Figure 2. PCB magnetic field mapping and highlighted principal nets causing most of the emissions.

EMC simulation software first requires reading in the PCB design data. Then, using one of the layout interfaces provided, the simulation software performs the following steps automatically:

• Time-domain currents are simulated for all (or, if requested, a subset) of the nets.
• A fast Fourier transform is performed to provide the harmonic content of the time-domain waveshapes.
• Nets are numerically broken down into elemental antenna segments, accounting for segment location and direction.
• Emissions from pins and vias as well as from the transmission line nets are accounted for. This includes emis- sions detected even when the PCB is clad in copper sheets (i.e., stripline).
• Using the law of Biot-Savart, the values of H x, Hy, and Hz are computed by integration over all current elements at any arbitrary height (usually 5 mm) above the board.
• Highly radiating hot areas are mapped at each frequency.
• Nets that are the principal contributors to establishment of the hot areas are highlighted, which identifies the wires producing the emissions.
• Termination scenarios can be performed to determine appropriate solutions.

EMC problems cannot be solved, however, without addressing signal integrity issues.

Causes of Emissions

 

Figure 3. Voltage waveshapes at all pins on the dominant net.

Three principal causes of emissions are signal-related: pulse-repetition frequency (i.e., clock frequency), signal edge rate, and signal ringing due to mismatch. High spectral values attributed to these causes are shown in Figure 1. For example:

• If the clock period is 50 nanoseconds (i.e., 50 ns/cycle), the fundamental harmonic is 20 MHz.
• High clock rates cause dominant spectral values at corresponding frequencies. If the signal is symmetrical in time, odd harmonics, such as 20, 60, or 100 MHz, will occur. Harmonics at 40 or 80 MHz, for example, will be nonexistent or (in practice) much smaller. The magnitude of these harmonics depends upon the rate of switching charge transferred (i.e., the edge rate), and therefore the magnitude depends upon the technology employed. Edge rate is largely technology dependent.
• If a voltage signal edge rate (i.e., the signal rise or fall time) is 2.5 nanoseconds, expect capacitive charging (i.e., unidirectional current transfer) to last for this duration. This corresponds to a half cycle of the current waveform. Therefore, for the full 5-nanosecond cycle, an associated fundamental current harmonic is expected at 200 MHz. Currents cause emissions, and so significant emissions can be expected at that frequency. Reducing the slope of the leading edge reduces the rate of charge transfer (i.e., current strength) and resulting emissions.
• Ringing due to termination mismatch is identified by signals superimposed upon the voltage waveform. The period of oscillation depends upon both the pin-to-pin length from driver to terminations and the velocity of signal propagation. It is preferable to see serious ringing die down (due to attenuation over several multiple pin-to-pin traverses of the signal) during the time of the rising edge. Therefore, a slow edge keeps the signal peak from being deformed (i.e., overshoot and undershoot violations that cause false triggering) by excessive ringing.

Hot Areas

 

Figure 4. Current waveshapes within all tracks along the dominant net.

Figure 2 shows the highly radiating regions on a PCB. The two most significant nets causing the problem are highlighted. Note that the maximum magnetic field they produce is 97.17 dBuA/m. Figures 3 and 4 show the voltage and current waveforms of the most significant (orange) net at all connected pins. The steep rising edge is caused by the semiconductor technology edge rate combined with the ringing due to reflections from the net terminations. The bump on the rising edge indicates where the effect of ringing kicks in, and the signal overshoot is obvious.

The effective voltage edge rate is approximately 5 nanoseconds. Correspondingly, the current cycle time at the leading edge (which looks almost like a sine wave) is 10 nanoseconds. These observations correspond to emissions at 100 MHz. The emissions spectrum chart (Figure 1) shows a peak emission at the same frequency. It can be concluded, therefore, that this emission is the result of the rapid edge rate (due to the combination of the semiconductor technology and the transmission-line ringing) rather than the pulse-repetition frequency.

EMC Brain Surgery

 

Figure 5. A 50-W resistor added in series with the driver pin (left) and a 75-W resistor added in parallel with the receiver pin (right).

Adding ferrites and absorbing materials and tightly sealing enclosures is a ham-fisted approach to solving EMC problems. These techniques are akin to dipping a PCB into a bath of molten solder to certainly contain emissions! The elegant solution, of course, is to rectify the problem at the source. This approach is more like brain surgery using intraoperative technology.

 

Figure 6. Current waveforms reduced using a 25-W resistor in series with the driver pin.

In this example, the root cause of the emissions is the steep pulse edges. Just as ringing can be rectified by adding a matching resistor to terminations, modifying the edge rate can be accomplished by adding a series resistor at the driver pin. In a practical way, this can be viewed as a means of increasing the equivalent driver resistance- capacitance time constant, and thus slowing down the edge rate.

In fact, the driver resistor can also reduce ringing by absorbing most of the reflected signal upon its return from the termination. Figure 5 shows the effects of adding resistors to the driver and termination pins. By comparing Figure 3 and the left-hand graphic of Figure 5, it is apparent that the driver resistor reduced the edge rate significantly. In the right-hand graphic of Figure 5, a 75-W resistor was inserted parallel to the most-distant receiver. The edge rate is hardly affected (compared with Figure 3), and some ringing is still evident. The first peak occurs at the same time as the bump seen in the left-hand figure. Both of these events are clearly due to ringing. If necessary, this could be rectified by inserting matching resistors at the other terminations on the net. Another solution would be to replace the 75-W resistor with one of another value.

 

Figure 7. Reduced emissions with a 25-W resistor placed in series with the driver pin.

Creating and analyzing such emission reduction scenarios is simple with simulation software. For example, in the left-hand graphic of Figure 5, a 50-W resistor was inserted in series with the driver, and the bump on the rising edge is still evident due to the reflected signal. A comparison of Figures 4 and 6 indicates a significant reduction in the line currents experienced at the pulse edges. A comparison of Figures 2 and 7 shows a reduction of emissions due to the inclusion of the 25-W resistor. Other output data indicate a reduction of >2 dBuA/m. Increasing the resistor to 50 W reduces currents an additional 3 dBuA/m. Although there is no direct and simple relationship between near-field and far-field values, in a given design environment, experience will dictate what field strengths are acceptable in practice.

Al Wexler, PhD, is president of Quantic EMC Inc. (Winnipeg, MB, Canada), a developer of EMC control software. He can be reached at wexler@quantic-emc.com.

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