A Better Model for Decoupling Clock Circuits

In PCB design, most electromagnetic emission failures result from clocks and their associated circuitry. Because clocks are so critical to the performance of the circuit, finding better ways to decouple the clocks, to provide superior noise control with very little cost increase, is an ongoing concern for designers.

Research into the problem of clock decoupling has already provided designers with some important information. For example, one study compares the effectiveness of three different capacitor types: a leaded ceramic, a leadless chip ceramic, and a distributed capacitor.¹ This study shows that the leaded ceramic provides decoupling at only the fundamental frequency, as its higher-frequency performance is limited by the inductance of the leads. The leadless chip capacitor performs better than the leaded part because of reduced inductance. Although it is not nearly as effective as the distributed capacitor, the leadless part is much less expensive and is representative of standard decoupling practice today. For applications requiring low differential-mode (DM) ripple on the V_^cc and ground, a distributed capacitor may be required despite its higher cost.

Another study investigates different capacitor values for varying frequencies of oscillators and loads.² In this study, only the leadless chip capacitors are considered because they are the most widely used type for multilayer boards. The results of this research are surprising. It shows that there is little difference in performance in the 0.01- to 0.1-µF range. However, values less than 0.01 µF are decreasingly effective at reducing ripple, with the 470-pF capacitor providing next to no decoupling at all. These results disprove the commonly held assumption that smaller capacitor values are better for higher-speed applications. According to this study, the best overall performer is the 0.01-µF capacitor.

Figure 1. (a) ideal capacitor vs. (b) practical capacitor.

To decouple ICs with capacitors, designers today build a localized reservoir of high-frequency energy for the circuit. The capacitor recharges from the bulk decoupling capacitor on the board or from the output capacitor of the power supply. Use of this design concept is the reason that large capacitors are placed on the inputs of power supplies. In essence, the capacitor helps decouple the IC from the main V^_cc, decreasing the amount of high-frequency ripple seen on the main bus (see ideal and practical capacitors in Figure 1a and 1b).

Figure 2. Practical capacitor attached to an ac source.

An ac analysis of the typical capacitor design illustrates several points (see Figure 2):

The classical approach toward decoupling used the CV = it model; however, research has shown that this equation can be misleading and can result in severe under-decoupling.² A decoupling capacitor that is too small (<1000 pF) does not have a low enough source impedance (when compared to the power bus on the board) to source energy to the IC. The result is that it provides no decoupling, and a high magnitude of differential-mode ripple is seen across the board.

Assuming that a proper choice of capacitor value is already made (the best choice is 0.01 µF for most applications), one of the most common ways that designers can improve filtering performance on the board is to add a ferrite bead in series with the V^_cc feed to the device. The intent of this addition is that the ferrite bead will act in conjunction with the filter capacitor and further decrease the DM noise on the V^_cc plane, which is the byproduct of the clock oscillator.

But is the increased cost of adding this ferrite bead justified by the improved performance? The authors of this article devised an experiment to answer this question, to measure the exact performance increase, if any. In the process, they discovered that by adding an additional capacitor along with the bead, they could achieve dramatic improvement in decoupling.

 

Experimental Design

In the circuits used for the decoupling experiment, clock oscillators generated constant and repeatable signatures: square-wave output with defined periods and rise times. The circuits required high-frequency input current, which showed up as current and voltage ripple on the input power leads. In this experiment, the oscillators were used as noise sources and were ideal for demonstrating the relative effectiveness of capacitive decoupling and filtering.

This experimental design had a number of logistical advantages. It did not require a special test facility, such as an open area test site or anechoic chamber, and could be performed on a benchtop in-house.

Oscillators were mounted on small, single-layer PCBs, and the V^_cc and ground planes were simulated using copper tape. With this setup, the leadless chip capacitors could be effectively used without the addition of leads, which would greatly degrade capacitor performance. The design also allowed for easy addition of the ferrite beads. Oscillators ranging in frequency from 33 to 100 MHz were used for the experiment. Although only 33-MHz data are shown here, similar results were seen for all oscillators tested.

Each circuit was powered with a 5-V dc power supply via approximately 2.5 feet of twisted-pair wire, which provided low source impedance for the oscillator power. The output of the oscillator drove one combination of resistor and capacitor in parallel. The resistor was 10 kW in parallel with a 10-pF load. These values were selected to simulate a clock driving on load, a commonplace configuration in the industry.

The researchers predicted that the results would support earlier research that showed the load on the oscillator was not a factor in determining filter performance. The load was connected directly across the output, minimizing coupling to the V^_cc and ground loop. A current probe was placed differentially around the V^_cc and return lines to mitigate the common-mode currents, which could confound these measurements.

Differential-mode current measurements were taken for the following configurations:

In addition to the first three configurations, the researchers created a fourth test board by applying one more component to the circuit with the ferrite bead, a capacitor at the supply side of the bead. The researchers called this configuration V-Pi, because the design was based on filtering the V^_cc pin of a clock with a filter in a p configuration (see Figure 3).

Figure 3. The V-Pi circuit for improved decoupling.

Experimental Results

The results generated by the experiment were relative measurements, which were taken with the same current probe in the same test setup (results are graphed in Figure 4a and 4b). The transfer impedance of the probe was not figured in, and the amplitudes were uncorrected and given in units of dBµV (see data set in Table I).

Figure 4a. Differential-mode ripple versus frequency.

Figure 4b. Differential-mode ripple versus frequency.

Frequency (MHz)		No decoupling (dBµV)	0.01-uF capacitor (dBµV)	0.01-µF capacitor plus ferrite bead (dBµV)	V-Pi (dBµV)
32.4		51	38	37	_
64.6		58	39	41	–
98.2		58	47	44	–
130.4		58	41	41	23
164		50	34	39	32
196.2		58	46	35	36
228.4		62	49	49	27
260.9		53	38	43	35
297.2		51	48	35	25
327.5		48	49	47	40
360.8		57	45	32	–
392.2		42	39	35	–
425.5		48	37	35	–
458.8		45	33	32	–
492.2		33	34	34	–
523.5		28	25	25	–
556.8		22	31	30	–
Table I. Summary of results with 33-MHz oscillators.

The probe used was a Tegam model 94111-1, a 5-W probe. Although the probe was usable above 500 MHz, the amplitudes of the harmonics of the fastest clock fell below the noise floor of the test setup, so minimal data above this frequency could be taken. The current probe was placed differentially around the lines to reject common-mode currents, so the actual differential current from the oscillator was 6 dB less than shown, and common-mode currents were not considered in this experiment. The measurement of common-mode currents was excluded not because it was deemed unimportant, but because the experiment focused on the reduction of only differential-mode noise through capacitive decoupling.

As expected, the experiment revealed that the lack of a decoupling capacitor resulted in significant differential-mode emissions on the power cable and that the addition of a 0.01-µF capacitor greatly reduced the DM emissions.

Unexpectedly, though, the experiment showed that the ferrite bead added in series with the V^_cc of the clock provided little or no improvement in the DM emissions. In act, at some frequencies, the emissions were actually enhanced when the bead was added.

Analysis

How do the experiment's results translate to multilayer circuit boards? For two-layer boards, the V-Pi model will result in a significant reduction of DM noise between V_cc and ground. For boards with four or more layers, the applicability of the results depends on the spacing between the V^_cc and ground planes. If V^_cc and ground are on adjacent layers, and a 6-mil spacing is used, the distributed capacitance provided by the power planes is about 150 pF/sq in. (This assumes a dielectric permittivity of 4 times e^_o.) As the spacing between the V_cc and ground increases, the distributed capacitance will decrease proportionally, increasing the bus impedance on the board. Therefore, for a six-layer stackup, such as the one shown in Figure 5a, the V-Pi configuration could be extremely effective due to the relatively high power distribution impedance. For a four-layer configuration, such as the one shown in Figure 5b, the V-Pi could still reduce DM noise, though not to the same degree.

Figure 5a and b. Representative stackups for (a) six-layer and (b) four-layer boards.

When properly implemented, decoupling capacitors reduce the amount of DM clock ripple between the V^_cc and ground planes by at least 10 dB. Although not required for all designs, capacitors offer an inexpensive way to increase reliability for high-speed applications. If additional DM reduction is required for the clock and related circuits, adding a ferrite bead in series with the V^_cc pin may provide improved results, but the improvement would not be great enough to justify the expense. However, by placing an additional capacitor on the ferrite side of the board, designers can achieve dramatic reduction of DM noise.

 

References

Charles Grasso is an EMC engineer at StorageTek (Louisville, CO). He has more than 12 years of experience in the field of EMC design, specializing in system architectural design and board-level design techniques for EMI control. He has worked on a wide range of products, from personal computers to large data storage systems. He may be reached by telephone at 303/673-2908 or fax at 303/661-7115.